中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.011 seconds)

    Interconnection system with flexible pins
    2.
    发明授权
    Interconnection system with flexible pins 有权

    公开(公告)号：US10408860B2

    公开(公告)日：2019-09-10

    申请号：US15475296

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Jorge A. Alvarez Gonzalez ,  Fernando Gonzalez Lenero ,  Antonio Zenteno Ramirez ,  Fernando Mendoza Hernandez

    IPC: G01R31/00 ,  G01R1/073 ,  H05K1/11 ,  G01R1/04 ,  H05K3/00

    Abstract: An embodiment includes a system comprising: a polymer substrate including a plurality of voids; and a plurality of metal pins; wherein a first pin, included within the plurality of metal pins, includes: (a)(i) first and second arms that couple to each other by way of an arcuate member, (a)(ii) a middle portion including a middle diameter, a proximal portion including a proximal diameter, and a distal portion including a distal diameter; wherein (b)(i) the middle portion is between the proximal and distal portions, (b)(ii) the middle diameter is less than the proximal and distal diameters, and (b)(iii) the proximal portion, but not the distal portion, is included within one of the plurality of voids. Other embodiments are described herein.

    FRAMEWORK INCLUDING AN INTERPOSER HAVING AN ATYPICAL SHAPE
    4.
    发明申请
    FRAMEWORK INCLUDING AN INTERPOSER HAVING AN ATYPICAL SHAPE 有权

    公开(公告)号：US20220094094A1

    公开(公告)日：2022-03-24

    申请号：US17303991

    申请日：2021-06-11

    Applicant: Intel Corporation

    Inventor： Ulises Encarnacion ,  Luis Ricardo Perez Corona ,  Ricardo Astro Bohorquez ,  Antonio Zenteno Ramirez ,  Maria J. Garcia Garcia De Leon

    IPC: H01R12/82

    Abstract: In one embodiment, an apparatus includes an integrated circuit (IC) socket and an interposer. The IC socket includes a cavity to receive an IC package including first and second sets of IC contacts, the cavity defined by a base including a set of IC socket interconnects and a frame extending from the base with at least one opening through the frame. The interposer includes a cavity portion disposed adjacent the base of the IC socket, an external portion extending from the cavity portion through one of the at least one opening, at least one connector disposed on the external portion, a first set of interposer interconnects to electrically couple each of the first set of IC contacts with a corresponding one of the set of IC socket interconnects, and a second set of interposer interconnects to electrically couple each of the second set of IC contacts with one of the at least one connector. Other embodiments are described and claimed.

    MODE SELECTIVE BALANCED ENCODED INTERCONNECT
    6.
    发明申请
    MODE SELECTIVE BALANCED ENCODED INTERCONNECT 审中-公开
    模式选择平衡编码互连

    公开(公告)号：US20160026597A1

    公开(公告)日：2016-01-28

    申请号：US14444616

    申请日：2014-07-28

    Applicant: INTEL CORPORATION

    Inventor： Michael W. Leddige ,  Stephen H. Hall ,  Chaitanya Sreerama ,  Olufemi B. Oluwafemi ,  Antonio Zenteno Ramirez ,  Maynard C. Falconer

    IPC: G06F13/42 ,  G06F13/20

    CPC classification number: G06F13/4221 ,  G06F13/20

    Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

    Abstract translation: 这里描述了一种装置。 该装置包括多个导体，其中至少一个导体是共模导体。 该装置还包括编码器，用于编码要在多个导体上传输的数据，其中共模导体的数据速度受到限制，并且其他导体的数据速度根据编码矩阵最大化。

Patent Agency Ranking