公开(公告)号：US20240292520A1

公开(公告)日：2024-08-29

申请号：US18437713

申请日：2024-02-09

申请人： Sumitomo Electric Device Innovations, Inc.

发明人： Ikuo Nakashima

IPC分类号： H05K1/02 ,  H01L23/498 ,  H05K1/16

CPC分类号： H05K1/0251 ,  H01L23/49822 ,  H05K1/162 ,  H05K2201/09645

摘要： A matching circuit board includes a first substrate, a second substrate, and a third substrate. The first substrate includes a first insulator, a first metal pattern, and first conductive vias. The second substrate includes a second insulator, a second metal pattern, and second conductive vias. The third substrate includes a third insulator and a third metal pattern. A capacitor is constituted by the first metal pattern, the second insulator, and the second metal pattern, and a capacitor is constituted by the first metal pattern, the first insulator, and the third metal pattern. The second metal pattern is electrically connected to the third metal pattern through the second conductive vias and the first conductive vias. The first metal pattern is separated from the first conductive vias to be positioned inside the first conductive vias, and is insulated from the first conductive vias.

公开(公告)号：US20180310418A1

公开(公告)日：2018-10-25

申请号：US16019452

申请日：2018-06-26

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Stig KALLMAN ,  Tomas BERGSTEN

IPC分类号： H05K3/42 ,  C25D5/02 ,  H05K1/09 ,  H05K1/11

CPC分类号： H05K3/429 ,  C25D5/02 ,  C25D5/022 ,  H05K1/092 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09645 ,  H05K2203/0713

摘要： The embodiments herein relate to an apparatus and medium for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The apparatus and medium implement a step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.

公开(公告)号：US20180295718A1

公开(公告)日：2018-10-11

申请号：US16007410

申请日：2018-06-13

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC分类号： H05K1/02 ,  H01L23/498 ,  H01R12/71 ,  H05K3/42 ,  H05K1/11

CPC分类号： H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

公开(公告)号：US20180177049A1

公开(公告)日：2018-06-21

申请号：US15380054

申请日：2016-12-15

申请人： NXP USA, INC.

发明人： Michael B. Vincent ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： H05K1/115 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/145 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1178 ,  H05K2203/1316 ,  H05K2203/1327 ,  Y10T29/49165

摘要： A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

公开(公告)号：US09960079B2

公开(公告)日：2018-05-01

申请号：US13897202

申请日：2013-05-17

申请人： Intel Corporation

发明人： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/48 ,  H01L23/64 ,  H01L23/66 ,  H05K1/11 ,  H05K1/16 ,  H01L23/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42

CPC分类号： H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

公开(公告)号：US20170343204A1

公开(公告)日：2017-11-30

申请号：US15681989

申请日：2017-08-21

申请人： Molex, LLC

发明人： Yi-Tse HO

IPC分类号： F21V29/83 ,  F21K9/232 ,  H05K3/18 ,  F21V29/77 ,  H05K1/02 ,  F21V19/00 ,  F21Y2107/40 ,  H05K3/38 ,  H05K3/10 ,  H05K3/00 ,  F21V3/00 ,  F21Y2115/10

CPC分类号： F21V29/83 ,  F21K9/232 ,  F21V3/00 ,  F21V19/0055 ,  F21V29/77 ,  F21Y2107/40 ,  F21Y2115/10 ,  H05K1/0204 ,  H05K1/0209 ,  H05K1/0284 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/182 ,  H05K3/381 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/09154 ,  H05K2201/09645 ,  H05K2201/09781 ,  H05K2201/09854 ,  H05K2201/10106 ,  H05K2201/10113 ,  H05K2201/10287 ,  H05K2201/10409 ,  H05K2203/107

摘要： An illumination device comprises a holder, a plurality of light emitting elements, a translucent cover and a lamp cap structure. The holder comprises a heat dissipating base body and a carrying unit. The carrying unit is connected to a top portion of the heat dissipating base body and comprises a carrying base body, a circuit pattern and a heat dissipating pattern, the circuit pattern and the heat dissipating pattern are directly formed to a surface of the carrying base body, the circuit pattern has a plurality of mounting positions, the heat dissipating pattern at least extends from a region close to the mounting position to a region where the heat dissipating pattern can contact the heat dissipating base body. The plurality of light emitting elements are respectively provided at the plurality of the mounting positions and establish an electrical connection with the circuit pattern.

公开(公告)号：US09807867B2

公开(公告)日：2017-10-31

申请号：US15016147

申请日：2016-02-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K3/00 ,  H05K3/42 ,  H05K3/40 ,  H05K1/11

CPC分类号： H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/42 ,  H05K3/423 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09645

摘要： A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.

公开(公告)号：US09603255B2

公开(公告)日：2017-03-21

申请号：US15048510

申请日：2016-02-19

申请人： NextGin Technology BV

发明人： J. A. A. M. Tourne

IPC分类号： H01K3/10 ,  H05K3/10 ,  H05K1/02 ,  H05K3/40

CPC分类号： H05K3/107 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/403 ,  H05K3/42 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09645 ,  H05K2201/09854

摘要： A method for producing a printed circuit board is disclosed. In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.

公开(公告)号：US20160378215A1

公开(公告)日：2016-12-29

申请号：US14752642

申请日：2015-06-26

申请人： INTEL CORPORATION

发明人： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang ,  Jose Diego Guillen Gonzalez ,  Beom-Taek Lee

IPC分类号： G06F3/041 ,  H01P3/08

CPC分类号： H01P3/08 ,  H01P5/028 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09645 ,  H05K2201/09854

摘要： Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.

摘要翻译： 提供延伸穿过印刷电路板（PCB）或其它基板的至少一部分的通孔的紧凑布置的技术和机构。 在一个实施例中，衬底包括电介质材料和形成至少部分延伸穿过电介质材料的孔区的侧壁结构。 孔区域邻接第一通孔和第二通孔中的每一个，并且还位于第一通孔和第二通孔之间。 在另一个实施例中，第一通孔被耦合以交换差分信号对的第一信号，并且第二通孔被耦合以交换相同差分信号对的第二信号。

公开(公告)号：US09526184B2

公开(公告)日：2016-12-20

申请号：US13537361

申请日：2012-06-29

申请人： Roy J. Lecesse

发明人： Roy J. Lecesse

IPC分类号： H05K3/42 ,  C23C18/38 ,  C23C18/16

CPC分类号： H05K3/429 ,  C23C18/165 ,  C23C18/1653 ,  C23C18/38 ,  H05K3/42 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09645 ,  H05K2203/0207 ,  H05K2203/1476

摘要： A method and system for constructing a printed circuit board with multifunctional holes. A first conductive material is deposited into a hole in a substrate to form a first plating on an inner surface of the hole. At least one outer portion of the hole is modified to have a larger diameter than the original hole and to remove the first conductive material from that outer portion. A seed material is deposited into the modified hole. An etchant is applied to the hole to non-mechanically remove the first conductive material from the unmodified portion of the hole. Another conductive material is deposited to into the modified hole that adheres to the seed material in the modified outer portion via to form a second plating at the outer portion.

摘要翻译： 一种用于构造具有多功能孔的印刷电路板的方法和系统。 将第一导电材料沉积在基底中的孔中以在孔的内表面上形成第一电镀。 孔的至少一个外部部分被修改为具有比原始孔更大的直径并且从该外部部分移除第一导电材料。 种子材料沉积到修改的孔中。 将蚀刻剂施加到孔以从孔的未修改部分非机械地去除第一导电材料。 另一种导电材料被沉积到修饰的孔中，该修饰的孔粘附在改进的外部部分通孔中的种子材料上，以在外部部分形成第二电镀。