公开(公告)号：US20190027604A1

公开(公告)日：2019-01-24

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： CHEN-GUAN LEE ,  WALID M. HAFEZ ,  JOODONG PARK ,  CHIA-HONG JAN ,  HSU-YU CHANG

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US20200006509A1

公开(公告)日：2020-01-02

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/764

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US20180374927A1

公开(公告)日：2018-12-27

申请号：US15778306

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  CHIA-HONG Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

公开(公告)号：US20200043914A1

公开(公告)日：2020-02-06

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  RAHUL RAMASWAMY ,  NIDHI NIDHI ,  CHEN-GUAN LEE

IPC: H01L27/06 ,  H01L27/088 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：US20180350932A1

公开(公告)日：2018-12-06

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/764

CPC classification number: H01L29/42376 ,  B82Y10/00 ,  H01L21/32133 ,  H01L21/764 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or J-shape, for example.