公开(公告)号：US20180151474A1

公开(公告)日：2018-05-31

申请号：US15576364

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： YI WEI CHEN ,  KINYIP PHOA ,  NIDHI NIDHI ,  JUI-YEN LIN ,  KUN-HUAN SHIH ,  XIAODONG YANG ,  WALID M. HAFEZ ,  CURTIS TSAI

IPC: H01L23/48 ,  H01L49/02 ,  H01L27/12 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

公开(公告)号：US20200043914A1

公开(公告)日：2020-02-06

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  RAHUL RAMASWAMY ,  NIDHI NIDHI ,  CHEN-GUAN LEE

IPC: H01L27/06 ,  H01L27/088 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：US20170103923A1

公开(公告)日：2017-04-13

申请号：US15127839

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： NIDHI NIDHI ,  CHIA-HONG JAN ,  ROMAN W. OLAC-VAW ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  WALID M. HAFEZ ,  RAHUL RAMASWAMY

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.

公开(公告)号：US20200219772A1

公开(公告)日：2020-07-09

申请号：US16239059

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： RAHUL RAMASWAMY ,  NIDHI NIDHI ,  WALID M. HAFEZ ,  JOHANN C. RODE ,  PAUL FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANSAPTAK DASGUPTA

IPC: H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/872 ,  H01L29/66

Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).

公开(公告)号：US20170155004A1

公开(公告)日：2017-06-01

申请号：US15127207

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： KINYIP PHOA ,  NIDHI NIDHI ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  YI WEI CHEN

IPC: H01L31/0224 ,  H02S40/38 ,  H01L31/18 ,  H01L31/028 ,  H01L31/05 ,  H01L31/056 ,  H01L31/068

CPC classification number: H01L31/022458 ,  H01L31/022475 ,  H01L31/028 ,  H01L31/047 ,  H01L31/0516 ,  H01L31/056 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/1884 ,  H02S40/38 ,  Y02E10/52 ,  Y02E10/547

Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.