公开(公告)号：US20240004659A1

公开(公告)日：2024-01-04

申请号：US17853087

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Michael LeMay ,  Dan Baum ,  Joseph Cihula ,  Joao Batista Correa Gomes Moreira ,  Anjo Lucas Vahldiek-Oberwagner ,  Scott Constable ,  Andreas Kleen ,  Konrad Lai ,  Henrique de Medeiros Kawakami ,  David M. Durham

IPC: G06F9/30

CPC classification number: G06F9/3016

Abstract: Techniques for an instruction for a Runtime Call operation are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of an opcode, the opcode to indicate execution circuitry is to execute a no operation when a runtime call destination equals a predetermined value; and execute an indirect call with the runtime call destination as a destination address when the runtime call destination does not equal the predetermined value. Other examples are described and claimed.

公开(公告)号：US11249761B2

公开(公告)日：2022-02-15

申请号：US16934003

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US12175246B2

公开(公告)日：2024-12-24

申请号：US18460497

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US11954489B2

公开(公告)日：2024-04-09

申请号：US17549363

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US20230393769A1

公开(公告)日：2023-12-07

申请号：US17957814

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Sergej Deutsch ,  Dan Baum

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A processor includes a register to store an encoded pointer for a memory address within a first memory allocation of a plurality of memory allocations in a memory region of a memory. The processor further includes circuitry to receive a memory operation request based on the encoded pointer and to obtain a first tag of a plurality of tags stored in a table in the memory. Each memory allocation of the plurality of memory allocations is associated with a respective one of the plurality of tags stored in the table. The circuitry is to further obtain pointer metadata stored in the encoded pointer and to determine whether to perform a memory operation corresponding to the memory operation request based, at least in part, on a determination of whether the first pointer metadata corresponds to the first tag.

公开(公告)号：US11714648B2

公开(公告)日：2023-08-01

申请号：US17549221

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US11327754B2

公开(公告)日：2022-05-10

申请号：US16366941

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Dan Baum ,  Robert S. Chappell ,  Michael Espig ,  Varghese George ,  Alexander Heinecke ,  Christopher Hughes ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Ronen Zohar ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30 ,  G06F17/11 ,  G06F7/544 ,  G06F9/38 ,  G06F7/552

Abstract: Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

公开(公告)号：US11163565B2

公开(公告)日：2021-11-02

申请号：US16486960

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Mark J. Charney ,  Menachem Adelman ,  Barukh Ziv ,  Alexander Heinecke ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F17/16 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

公开(公告)号：US10896043B2

公开(公告)日：2021-01-19

申请号：US16146854

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Bret Toll ,  Alexander F. Heinecke ,  Christopher J. Hughes ,  Ronen Zohar ,  Michael Espig ,  Dan Baum ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F17/16 ,  G06F12/02 ,  G06F9/30 ,  G06F12/06 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/345

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US10719323B2

公开(公告)日：2020-07-21

申请号：US16144902

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.