公开(公告)号：US20170109230A1

公开(公告)日：2017-04-20

申请号：US14883610

申请日：2015-10-14

Applicant: INTEL CORPORATION

Inventor： Debaleena DAS

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411

Abstract: Provided are an apparatus and method for generating common locator bits to locate a device or column error during error correction operation for a memory subsystem having memory modules, each including a plurality of memory devices. Error detection logic generates common locator bits from device bits in a plurality of memory devices in one of the memory modules. The error detection logic uses the common locator bits to locate a column across at least two of the memory devices having an error when there is a column error and to locate a memory device in the devices having an error when there is a device error. A same of the common locator bits are used to locate both one of the columns and the memory devices having errors. Error correction is performed on the located memory device or column having the error.

公开(公告)号：US20180196709A1

公开(公告)日：2018-07-12

申请号：US15912450

申请日：2018-03-05

Applicant: INTEL CORPORATION

Inventor： Debaleena DAS ,  Rajat AGARWAL ,  Brian S. MORRIS

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US20180181336A1

公开(公告)日：2018-06-28

申请号：US15392912

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： John V. LOVELACE ,  Sreenivas MANDAVA ,  Debaleena DAS

IPC: G06F3/06

CPC classification number: G06F21/79 ,  G06F11/1048 ,  G06F2221/2143

Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

公开(公告)号：US20180024878A1

公开(公告)日：2018-01-25

申请号：US15724222

申请日：2017-10-03

Applicant: Intel Corporation

Inventor： Debaleena DAS ,  Bill NALE ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.