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    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
    3.
    发明申请
    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION 审中-公开
    大容量存储器重新引导的指令和逻辑

    公开(公告)号：US20160092222A1

    公开(公告)日：2016-03-31

    申请号：US14496113

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

    Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

    Abstract translation: 处理器包括前端，解码器，分配器和退休单元。 解码器包括用于识别终点范围（EOLR）指示符的逻辑。 EOLR指示符指定体系结构寄存器和不使用体系结构寄存器的代码中的位置。 分配器包括基于EOLR指示器扫描架构寄存器到物理寄存器的映射的逻辑。 分配器还包括生成用于将体系结构寄存器与物理寄存器取消关联的请求的逻辑。 退休单位包括将架构寄存器与物理寄存器取消关联的逻辑。

    WEIGHT-SHIFTING MECHANISM FOR CONVOLUTIONAL NEURAL NETWORKS
    5.
    发明申请
    WEIGHT-SHIFTING MECHANISM FOR CONVOLUTIONAL NEURAL NETWORKS 审中-公开
    用于交互式神经网络的重量分配机制

    公开(公告)号：US20160026912A1

    公开(公告)日：2016-01-28

    申请号：US14337979

    申请日：2014-07-22

    Applicant: Intel Corporation

    Inventor： Ayose J. Falcon ,  Marc Lupon ,  Enric Herrero Abellanas ,  Pedro Lopez ,  Fernando Latorre ,  Frederico C. Pratas ,  Georgios Tournavitis

    IPC: G06N3/06 ,  G06N3/08

    CPC classification number: G06N3/06 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08

    Abstract: A processor includes a processor core and a calculation circuit. The processor core includes logic determine a set of weights for use in a convolutional neural network (CNN) calculation and scale up the weights using a scale value. The calculation circuit includes logic to receive the scale value, the set of weights, and a set of input values, wherein each input value and associated weight of a same fixed size. The calculation circuit also includes logic to determine results from convolutional neural network (CNN) calculations based upon the set of weights applied to the set of input values, scale down the results using the scale value, truncate the scaled down results to the fixed size, and communicatively couple the truncated results to an output for a layer of the CNN.

    Abstract translation: 处理器包括处理器核心和计算电路。 处理器核心包括确定用于卷积神经网络（CNN）计算的一组权重的逻辑，并使用比例值来放大权重。 计算电路包括接收比例值，权重集合和一组输入值的逻辑，其中每个输入值和相同固定大小的相关权重。 计算电路还包括基于应用于输入值集合的权重集合来确定卷积神经网络（CNN）计算结果的逻辑，使用比例值缩小结果，将缩小的结果截断为固定大小， 并将截断的结果通信地耦合到CNN的层的输出。

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