公开(公告)号：US20190206110A1

公开(公告)日：2019-07-04

申请号：US15858396

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： JOHN G. GIERACH ,  TRAVIS SCHLUESSLER ,  THOMAS F. RAOUX ,  PENG GUO

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06F9/38 ,  G06T1/20 ,  G06T2210/52

Abstract: An apparatus and method for splitting shaders. For example, one embodiment of a method comprises: receiving a request for compilation of a shader in a graphics processing environment; determining whether there is sufficient work associated with the shader to justify splitting the shader into two or more blocks of program code; evaluating the program code of the shader to identify dependencies between the blocks of program code if there is sufficient work; subdividing the shader into the two or more blocks in accordance with the identified dependencies; and individually executing the two or more blocks of code on a graphics processor. In addition, one embodiment includes the operations of determining whether any of the regions that can be subdivided are likely to run faster with different machine configurations than if the shader is executed without being subdivided, and subdividing the shader only for those regions that are likely to run faster with different machine configurations.

公开(公告)号：US20200043218A1

公开(公告)日：2020-02-06

申请号：US16056222

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  WON-JONG LEE ,  GABOR LIKTOR ,  JOHN G. GIERACH ,  PAWEL MAJEWSKI ,  PRASOONKUMAR SURTI ,  CARSTEN BENTHIN ,  Sven WOOP ,  THOMAS RAOUX

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/80

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US20160364827A1

公开(公告)日：2016-12-15

申请号：US14738660

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： TRAVIS T. SCHLUESSLER ,  JOHN G. GIERACH

IPC: G06T1/20 ,  G06F9/48 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F15/16 ,  G06T1/60

Abstract: A mechanism is described for facilitating configuration of computing engines based on runtime workload measurements at computing devices. A method of embodiments, as described herein, includes detecting a work unit corresponding to a workload, and collecting metrics relating to the work unit, where the metrics to indicate one or more characteristics of the work unit. The method may further include evaluating the one or more characteristics based on one or more configuration parameters relating to computing resources, and generating, based on evaluating of the one or more characteristics, a configuration plan specific to the work unit and applicable to one or more subsequent work units that are similar to the work unit. The method may further include applying and executing the configuration plan at a computing device upon execution of the one or more subsequent work units.

Abstract translation: 描述了一种机制，用于基于计算设备上的运行时工作负载测量来促进计算引擎的配置。 如本文所述的实施例的方法包括检测对应于工作负载的工作单元，以及收集与工作单元相关的指标，其中指示工作单元的一个或多个特性的度量。 该方法还可以包括基于与计算资源相关的一个或多个配置参数来评估所述一个或多个特征，以及基于对所述一个或多个特性的评估，生成特定于所述工作单元并且适用于一个或多个 与工作单位相似的后续工作单位。 该方法还可以包括在执行一个或多个后续工作单元时在计算设备处应用和执行配置计划。