公开(公告)号：US20180350932A1

公开(公告)日：2018-12-06

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/764

CPC classification number: H01L29/42376 ,  B82Y10/00 ,  H01L21/32133 ,  H01L21/764 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or J-shape, for example.

公开(公告)号：US20200006509A1

公开(公告)日：2020-01-02

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/764

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US20180151474A1

公开(公告)日：2018-05-31

申请号：US15576364

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： YI WEI CHEN ,  KINYIP PHOA ,  NIDHI NIDHI ,  JUI-YEN LIN ,  KUN-HUAN SHIH ,  XIAODONG YANG ,  WALID M. HAFEZ ,  CURTIS TSAI

IPC: H01L23/48 ,  H01L49/02 ,  H01L27/12 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.