公开(公告)号：US20180151474A1

公开(公告)日：2018-05-31

申请号：US15576364

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： YI WEI CHEN ,  KINYIP PHOA ,  NIDHI NIDHI ,  JUI-YEN LIN ,  KUN-HUAN SHIH ,  XIAODONG YANG ,  WALID M. HAFEZ ,  CURTIS TSAI

IPC: H01L23/48 ,  H01L49/02 ,  H01L27/12 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

公开(公告)号：US20160035735A1

公开(公告)日：2016-02-04

申请号：US14880814

申请日：2015-10-12

Applicant: INTEL CORPORATION

Inventor： WALID M. HAFEZ ,  CHIA-HONG JAN ,  CURTIS TSAI ,  JOODONG PARK ,  JENG-YA D. YEH

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

Abstract translation: 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。

公开(公告)号：US20160197082A1

公开(公告)日：2016-07-07

申请号：US14912890

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JOODONG PARK ,  GOPINATH BHIMARASETTI ,  RAHUL RAMASWAMY ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JENG-YA D. YEH ,  CURTIS TSAI

IPC: H01L27/108

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

Abstract translation: 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。 栅电极堆叠被配置为与半导体鳍片的窄鳍区域共形，栅电极堆叠包括设置在栅介质层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域布置在相应的一个宽鳍片区域中。

公开(公告)号：US20160211369A1

公开(公告)日：2016-07-21

申请号：US14913326

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： CHIA-HONG JAN ,  WALID M. HAFEZ ,  CURTIS TSAI ,  JENG-YA D. YEH ,  JOODONG PARK

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。