公开(公告)号：US20180151474A1

公开(公告)日：2018-05-31

申请号：US15576364

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： YI WEI CHEN ,  KINYIP PHOA ,  NIDHI NIDHI ,  JUI-YEN LIN ,  KUN-HUAN SHIH ,  XIAODONG YANG ,  WALID M. HAFEZ ,  CURTIS TSAI

IPC: H01L23/48 ,  H01L49/02 ,  H01L27/12 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

公开(公告)号：US20170155004A1

公开(公告)日：2017-06-01

申请号：US15127207

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： KINYIP PHOA ,  NIDHI NIDHI ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  YI WEI CHEN

IPC: H01L31/0224 ,  H02S40/38 ,  H01L31/18 ,  H01L31/028 ,  H01L31/05 ,  H01L31/056 ,  H01L31/068

CPC classification number: H01L31/022458 ,  H01L31/022475 ,  H01L31/028 ,  H01L31/047 ,  H01L31/0516 ,  H01L31/056 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/1884 ,  H02S40/38 ,  Y02E10/52 ,  Y02E10/547

Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.