公开(公告)号：US12229867B2

公开(公告)日：2025-02-18

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike MacPherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US12101475B2

公开(公告)日：2024-09-24

申请号：US17127544

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Brinda Ganesh ,  Nilesh Jain ,  Sumit Mohan ,  Faouzi Kossentini ,  Jill Boyce ,  James Holland ,  Zhijun Lei ,  Chekib Nouira ,  Foued Ben Amara ,  Hassene Tmar ,  Sebastian Possos ,  Craig Hurst

IPC: H04N19/114 ,  H04N19/154

CPC classification number: H04N19/114 ,  H04N19/154

Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：US12041250B2

公开(公告)日：2024-07-16

申请号：US16739584

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Basel Salahieh

IPC: H04N19/82 ,  H04N19/132 ,  H04N19/40 ,  H04N21/2365 ,  H04N21/4402

CPC classification number: H04N19/40 ,  H04N19/132 ,  H04N21/2365 ,  H04N21/4402

Abstract: An example apparatus for transcoding multi-dimensional video includes a multi-dimensional video decoder to decode a first bitstream of multi-dimensional video. The apparatus also includes a transcoder to transcode the decoded first bitstream to generate transcoded multi-dimensional data. The apparatus also further includes a multi-dimensional video encoder to generate a second bitstream based on the transcoded multi-dimensional data.

公开(公告)号：US11863731B2

公开(公告)日：2024-01-02

申请号：US17139738

申请日：2020-12-31

Applicant: Intel Corporation

Inventor： Eyal Ruhm ,  Jill Boyce ,  Asaf J. Shenberg

IPC: H04N13/161

CPC classification number: H04N13/161

Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.

公开(公告)号：US11722653B2

公开(公告)日：2023-08-08

申请号：US17217588

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Basel Salahieh ,  Sumit Bhatia ,  Jill Boyce

IPC: H04N13/282 ,  H04N19/597 ,  H04N13/351 ,  G06T7/593 ,  G06T5/50 ,  H04N13/156 ,  H04N13/161

CPC classification number: H04N13/282 ,  G06T5/50 ,  G06T7/593 ,  H04N13/156 ,  H04N13/161 ,  H04N13/351 ,  H04N19/597 ,  G06T2207/20221

Abstract: An embodiment of an image processor for immersive video includes technology to re-order patches from a plurality of views based on one or more of relative position and orientation related information for a desired synthesized view, select a set of views to be used in each view synthesis pass, perform two or more view synthesis passes for the synthesized view to provide two or more intermediate view synthesis results, and mask and merge the two or more intermediate view synthesis results to provide a final view synthesis result. Other embodiments are disclosed and claimed.

公开(公告)号：US20230067541A1

公开(公告)日：2023-03-02

申请号：US17795178

申请日：2021-04-15

Applicant: INTEL CORPORATION

Inventor： Jill Boyce ,  Palanivel Guruva Reddiar ,  Praveen Prasad

IPC: G06V10/25 ,  G06V20/40 ,  G06V40/16 ,  G06T3/40

Abstract: Devices and techniques related to implementing patch based video coding for machines are discussed. Such patch based video coding includes detecting regions of interest in a frame of video, extracting the detected regions of interest to one or more atlases absent the frame at a resolution not less than the resolution of the regions of interest, and encoding the one or more atlases to a bitstream.

公开(公告)号：US20220159298A1

公开(公告)日：2022-05-19

申请号：US17440534

申请日：2020-05-14

Applicant: INTEL CORPORATION

Inventor： Jill Boyce

IPC: H04N19/597 ,  H04N19/159 ,  G06T7/80 ,  H04N19/124

Abstract: Techniques related to immersive video coding are discussed and include immersive video sequences and output units for random access to the immersive video, coding improvements for camera parameters coding, and coding efficiency improvements for atlas parameters.

公开(公告)号：US20210360267A1

公开(公告)日：2021-11-18

申请号：US17333772

申请日：2021-05-28

Applicant: Intel Corporation

Inventor： Jill Boyce

IPC: H04N19/196 ,  H04N19/70 ,  H04N19/463 ,  H04N19/42 ,  H04N19/136

Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

公开(公告)号：US11151769B2

公开(公告)日：2021-10-19

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike Macpherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T17/20 ,  G06N3/08 ,  G06T15/40

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20210090327A1

公开(公告)日：2021-03-25

申请号：US17112792

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Soethiha Soe ,  Selvakamur Panneer ,  Adam Lake ,  Nilesh Jain ,  Deepak Vembar ,  Glen J. Anderson ,  Varghese George ,  Carl Marshall ,  Scott Janus ,  Saurabh Tangri ,  Karthik Veeramani ,  Prasoonkumar Surti

IPC: G06T17/00 ,  G06N3/04 ,  G06N3/08 ,  G06T7/20 ,  G06K9/72 ,  G06F3/01 ,  G06K9/62

Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.