公开(公告)号：US11264338B2

公开(公告)日：2022-03-01

申请号：US15934191

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Ananth Prabhakumar ,  Krishna Srinivasan ,  Arnab Sarkar

IPC: H01L23/00 ,  H01L23/525 ,  H01L23/498 ,  H01L23/64

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

公开(公告)号：US10204851B2

公开(公告)日：2019-02-12

申请号：US15900696

申请日：2018-02-20

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US10658279B2

公开(公告)日：2020-05-19

申请号：US16261475

申请日：2019-01-29

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US09922916B2

公开(公告)日：2018-03-20

申请号：US15174921

申请日：2016-06-06

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.