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公开(公告)号：US20180024925A1
公开(公告)日：2018-01-25
申请号：US15214895
申请日：2016-07-20
Applicant: INTEL CORPORATION
Inventor： Raanan Sade , Joseph Nuzman , Stanislav Shwartsman , Igor Yanover , Liron Zur
IPC: G06F12/0815 , G06F12/0893
CPC classification number: G06F12/0815 , G06F12/0833 , G06F12/0893 , G06F2212/1016 , G06F2212/60 , G06F2212/62
Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.
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公开(公告)号：US11915000B2
公开(公告)日：2024-02-27
申请号：US18160600
申请日：2023-01-27
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Raanan Sade , Liron Zur , Igor Yanover , Joseph Nuzman
CPC classification number: G06F9/30145 , G06F9/30098 , G06F9/544 , G06F9/546 , G06F11/3037 , G06F11/348
Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
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Patent Agency Ranking
公开(公告)号：US11544062B2
公开(公告)日：2023-01-03
申请号：US16833596
申请日：2020-03-28
Applicant: Intel Corporation
Inventor： Raanan Sade , Igor Yanover , Stanislav Shwartsman , Muhammad Taher , David Zysman , Liron Zur , Yiftach Gilad
Abstract: An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.
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公开(公告)号：US20160070651A1
公开(公告)日：2016-03-10
申请号：US14481266
申请日：2014-09-09
Applicant: Intel Corporation
Inventor： Stanislav Shwartsman , Robert S. Chappell , Ronak Singhal , Ryan L. Carlson , Raanan Sade , Omar M. Shaikh , Liron Zur , Yiftach Gilad
IPC: G06F12/08
CPC classification number: G06F12/0897 , G06F12/0862 , G06F2212/1021 , G06F2212/402 , G06F2212/602
Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.
Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。
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公开(公告)号：US12271735B2
公开(公告)日：2025-04-08
申请号：US18419059
申请日：2024-01-22
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Raanan Sade , Liron Zur , Igor Yanover , Joseph Nuzman
Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
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公开(公告)号：US10303605B2
公开(公告)日：2019-05-28
申请号：US15214895
申请日：2016-07-20
Applicant: INTEL CORPORATION
Inventor： Raanan Sade , Joseph Nuzman , Stanislav Shwartsman , Igor Yanover , Liron Zur
IPC: G06F12/00 , G06F13/00 , G06F12/0815 , G06F12/0893
Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.
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7.发明授权公开(公告)号：US09558127B2
公开(公告)日：2017-01-31
申请号：US14481266
申请日：2014-09-09
Applicant: Intel Corporation
Inventor： Stanislav Shwartsman , Robert S. Chappell , Ronak Singhal , Ryan L. Carlson , Raanan Sade , Omar M. Shaikh , Liron Zur , Yiftach Gilad
IPC: G06F12/08
CPC classification number: G06F12/0897 , G06F12/0862 , G06F2212/1021 , G06F2212/402 , G06F2212/602
Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.
Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。
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