公开(公告)号：US09746903B2

公开(公告)日：2017-08-29

申请号：US14823994

申请日：2015-08-11

Applicant: Intel Corporation

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

公开(公告)号：US09558127B2

公开(公告)日：2017-01-31

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

公开(公告)号：US08924651B2

公开(公告)日：2014-12-30

申请号：US13864028

申请日：2013-04-16

Applicant: Intel Corporation

Inventor： Perry P. Tang ,  Hemant G. Rotithor ,  Ryan L. Carlson ,  Nagi Aboulenein

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/80

CPC classification number: G06F12/0862 ,  G06F15/8069 ,  G06F2212/502 ,  Y02D10/13

Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches.

Abstract translation: 本文描述了用于优化预取节流的装置和方法，其潜在地增强了性能，降低了功耗，并为从预取中受益的工作负载保持了正增益。 更具体地说，这里描述的优化允许考虑带宽拥塞和预取精度作为用于在预取生成源处节流的反馈。 结果，当拥塞低时，即使预取不准确，由于存在可用带宽，因此允许完全预取生成。 然而，当拥塞较高时，节流的确定下降到预取精度。 如果精度高，错失率低，则需要较少的节流，因为预取已被利用 - 性能正在提高。 然而，如果预取精度低错过率高，则需要更多的预取节流来节省功率，因为​​预取不被利用 - 性能并没有被大量预取提高。

公开(公告)号：US09606602B2

公开(公告)日：2017-03-28

申请号：US14318999

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

公开(公告)号：US20160070651A1

公开(公告)日：2016-03-10

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。