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    VIA BLOCKING LAYER
    1.
    发明申请
    VIA BLOCKING LAYER 审中-公开

    公开(公告)号：US20180174893A1

    公开(公告)日：2018-06-21

    申请号：US15898618

    申请日：2018-02-18

    Applicant: INTEL CORPORATION

    Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31

    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
    3.
    发明申请
    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE 审中-公开

    公开(公告)号：US20200312833A1

    公开(公告)日：2020-10-01

    申请号：US16902123

    申请日：2020-06-15

    Applicant: INTEL CORPORATION

    Inventor： WILFRED GOMES ,  MARK T. BOHR ,  RAJESH KUMAR ,  ROBERT L. SANKMAN ,  RAVINDRANATH V. MAHAJAN ,  WESLEY D. MC CULLOUGH

    IPC: H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065

    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

    VIA BLOCKING LAYER
    4.
    发明申请
    VIA BLOCKING LAYER 审中-公开

    公开(公告)号：US20170330794A1

    公开(公告)日：2017-11-16

    申请号：US15528427

    申请日：2014-12-23

    Applicant: INTEL CORPORATION

    Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

    IPC: H01L21/768 ,  H01L23/31 ,  H01L23/528

    CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

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