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    CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
    3.
    发明公开
    CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY 审中-公开

    公开(公告)号：US20230305978A1

    公开(公告)日：2023-09-28

    申请号：US17702271

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Mark C. Davis ,  Hong Jiang ,  Satish Damaraju

    IPC: G06F13/40

    CPC classification number: G06F13/4022 ,  G06F13/4009 ,  G06F13/4068

    Abstract: Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

    CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS
    7.
    发明公开
    CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS 审中-公开

    公开(公告)号：US20230305993A1

    公开(公告)日：2023-09-28

    申请号：US17702235

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Mark C. Davis ,  Ahmed Abou-Alfotouh ,  Hong Jiang

    IPC: G06F15/80 ,  G06F1/28

    CPC classification number: G06F15/80 ,  G06F1/28

    Abstract: Described herein is a modular parallel processor and associated manufacturing method in which the parallel processor is assembled from multiple chiplets that populate multiple chiplet slots of an active base chiplet die. The multiple chiplets are tested to determine characteristics of the chiplet, such as a number of functional units or a power consumption metric for the chiplet. The multiple chiplet slots can be configured to be populated by one or more chunks of multiple chiplets, where each chunk has a pre-determined collective value. The pre-determined collective value can be a total number of functional execution cores within a chunk or a collective power metric for the chunk.

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