公开(公告)号：US20190243577A1

公开(公告)日：2019-08-08

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  David B. CARLTON ,  Mark Anthony GOLEZ ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Sagar S. SIDHPURA ,  Sagar UPADHYAY ,  Neelesh VEMULA ,  Yogesh B. WAKCHAURE ,  Ye ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US20200089537A1

公开(公告)日：2020-03-19

申请号：US16689895

申请日：2019-11-20

Applicant: Intel Corporation

Inventor： Shirish BAHIRAT ,  David B. CARLTON ,  Jackson ELLIS ,  Jonathan M. HUGHES ,  David J. PELSTER ,  Neelesh VEMULA

IPC: G06F9/50 ,  G06F9/52 ,  G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F3/06

Abstract: A solid-state drive that can service multiple users or tenants and workloads (that is, multiple tenants) by enabling assigned bandwidth share of the solid-state drive across tenants is provided. The assigned bandwidth share is enabled for command submissions within a same assigned domain in addition to a weighted bandwidth share and quality of service control across different domains from all tenants.

公开(公告)号：US20190227749A1

公开(公告)日：2019-07-25

申请号：US16367638

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  David J. PELSTER ,  Donia SEBASTIAN ,  Curtis GITTENS ,  Xin GUO ,  Neelesh VEMULA ,  Varsha REGULAPATI ,  Naga Kiranmayee UPADHYAYULA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.