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    RESUMING STORAGE DIE PROGRAMMING AFTER POWER LOSS
    4.
    发明申请
    RESUMING STORAGE DIE PROGRAMMING AFTER POWER LOSS 审中-公开

    公开(公告)号：US20190103159A1

    公开(公告)日：2019-04-04

    申请号：US15720492

    申请日：2017-09-29

    申请人： INTEL CORPORATION

    发明人： Ali KHAKIFIROOZ ,  Rohit S. SHENOY ,  Pranav KALAVADE ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE

    IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C16/04

    摘要： Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

    UTILIZING NAND BUFFER FOR DRAM-LESS MULTILEVEL CELL PROGRAMMING
    6.
    发明申请
    UTILIZING NAND BUFFER FOR DRAM-LESS MULTILEVEL CELL PROGRAMMING 有权

    公开(公告)号：US20210151098A1

    公开(公告)日：2021-05-20

    申请号：US17133459

    申请日：2020-12-23

    申请人： Intel Corporation

    发明人： Shankar NATARAJAN ,  Suresh NAGARAJAN ,  Aliasgar S. MADRASWALA ,  Yihua ZHANG

    IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C29/42

    摘要： Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

    STORAGE SYSTEM WITH RECONFIGURABLE NUMBER OF BITS PER CELL
    9.
    发明申请
    STORAGE SYSTEM WITH RECONFIGURABLE NUMBER OF BITS PER CELL 审中-公开

    公开(公告)号：US20190227751A1

    公开(公告)日：2019-07-25

    申请号：US16370743

    申请日：2019-03-29

    申请人： Intel Corporation

    发明人： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Bharat M. PATHAK

    IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/10

    摘要： A memory device is designed to store data in multilevel storage cells (MLC storage cells). The memory device includes a controller that dynamically writes data to the storage cells according to a first MLC density or a second MLC density. The second density is less dense than the first density. For example, the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage.