公开(公告)号：US20210325952A1

公开(公告)日：2021-10-21

申请号：US17357479

申请日：2021-06-24

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US20210247829A1

公开(公告)日：2021-08-12

申请号：US17142149

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F1/3203 ,  G06F9/48 ,  G06F9/50 ,  G06N20/00 ,  G06F1/329

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US10223171B2

公开(公告)日：2019-03-05

申请号：US15081424

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Stephanie Labasan ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F9/50

Abstract: Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.

公开(公告)号：US10101786B2

公开(公告)日：2018-10-16

申请号：US14580150

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/50 ,  G06F1/18 ,  G06N99/00

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170357580A1

公开(公告)日：2017-12-14

申请号：US15628811

申请日：2017-06-21

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0646 ,  G06F12/023 ,  G06F2212/283

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

公开(公告)号：US12135981B2

公开(公告)日：2024-11-05

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11416281B2

公开(公告)日：2022-08-16

申请号：US16474978

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11061463B2

公开(公告)日：2021-07-13

申请号：US15689646

申请日：2017-08-29

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US10466754B2

公开(公告)日：2019-11-05

申请号：US14583237

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Ilya Sharapov ,  Richard J. Greco ,  Steve S. Sylvester ,  David N. Lombard

IPC: G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/50

Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

公开(公告)号：US20190286559A1

公开(公告)日：2019-09-19

申请号：US16433671

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC: G06F12/06 ,  G06F12/02

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.