公开(公告)号：US20150113255A1

公开(公告)日：2015-04-23

申请号：US14569454

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Shoumeng Yan ,  Xiaocheng Zhou ,  Hu Chen ,  Ying Gao ,  Sai Luo ,  Bratin Saha

IPC: G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1072 ,  G06F8/447 ,  G06F9/3863 ,  G06F9/3885 ,  G06F9/548 ,  G06F2212/657

Abstract: A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU 110 may be used to determine a GPU vtable if a GPU-side table exists. In another embodiment, a shared non-coherent region, which may not maintain data consistency, may be created within the shared virtual memory. The CPU and the GPU side data stored within the shared non-coherent region may have a same address as seen from the CPU and the GPU side. However, the contents of the CPU-side data may be different from that of GPU-side data as shared virtual memory may not maintain coherency during the run-time. In one embodiment, the vptr may be modified to point to the CPU vtable and GPU vtable stored in the shared virtual memory.

Abstract translation: 计算平台可以包括异构处理器（例如，CPU和GPU），以支持这些处理器之间的虚拟功能的共享。 在一个实施例中，如果GPU侧表存在，则用于从CPU 110访问共享对象的CPU侧vtable指针可用于确定GPU vtable。 在另一个实施例中，可以在共享虚拟存储器内创建可能不维持数据一致性的共享非相干区域。 存储在共享非相干区域内的CP​​U和GPU侧数据可以具有与CPU和GPU侧所见相同的地址。 然而，CPU侧数据的内容可能与GPU侧数据的内容不同，因为共享虚拟存储器可能在运行期间不能维持一致性。 在一个实施例中，可以修改vptr以指向存储在共享虚拟存储器中的CPU vtable和GPU vtable。

公开(公告)号：US10649899B2

公开(公告)日：2020-05-12

申请号：US15505879

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Sai Luo ,  Tin-Fook Ngai ,  Hu Chen ,  Xiaocheng Zhou ,  Chunxiao Lin ,  Kang Zhao

IPC: G06F12/00 ,  G06F12/0842 ,  G06F11/36 ,  G06F12/0831 ,  G06F12/0875

Abstract: A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

公开(公告)号：US10037284B2

公开(公告)日：2018-07-31

申请号：US13977010

申请日：2012-10-03

Applicant: Intel Corporation

Inventor： Sai Luo ,  Xin Zhou ,  Chunxiao Lin ,  Yingzhe Shen ,  Li Shang

IPC: G06F12/10 ,  G06F13/40 ,  G06F13/32 ,  G06F12/1081

CPC classification number: G06F12/1081 ,  G06F13/32 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.

公开(公告)号：US09710396B2

公开(公告)日：2017-07-18

申请号：US14503596

申请日：2014-10-01

Applicant: Intel Corporation

Inventor： Ying Gao ,  Hu Chen ,  Shoumeng Yan ,  Xiaocheng Zhou ,  Sai Luo ,  Bratin Saha

IPC: G06F12/02 ,  G06F12/109 ,  G06F9/46 ,  G06F9/54 ,  G06F15/167 ,  G06T1/20

CPC classification number: G06F12/109 ,  G06F9/466 ,  G06F9/544 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/20

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.