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    MEMORY TIMING CHARACTERIZATION CIRCUITRY
    4.
    发明公开
    MEMORY TIMING CHARACTERIZATION CIRCUITRY 审中-公开

    公开(公告)号：US20240319269A1

    公开(公告)日：2024-09-26

    申请号：US18124338

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram Kumar Krishnamurthy

    IPC: G01R31/317 ,  G01R31/3185

    CPC classification number: G01R31/31725 ,  G01R31/31713 ,  G01R31/318536

    Abstract: An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.

    Fused voltage level shifting latch
    5.
    发明授权
    Fused voltage level shifting latch 有权

    公开(公告)号：US10756736B2

    公开(公告)日：2020-08-25

    申请号：US16335092

    申请日：2017-08-30

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K19/0185 ,  H03K3/037

    Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

    Shared keeper and footer flip-flop
    6.
    发明授权
    Shared keeper and footer flip-flop 有权

    公开(公告)号：US10193536B2

    公开(公告)日：2019-01-29

    申请号：US15860562

    申请日：2018-01-02

    Applicant: INTEL CORPORATION

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

    IPC: H03K3/3562 ,  H03K3/037

    Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
    7.
    发明授权
    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权

    公开(公告)号：US09960753B2

    公开(公告)日：2018-05-01

    申请号：US15209531

    申请日：2016-07-13

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/356

    CPC classification number: H03K3/35625 ,  H03K3/356104

    Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
    8.
    发明授权
    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权
    低功耗全中断锁存器和主从触发器的装置和方法

    公开(公告)号：US09035686B1

    公开(公告)日：2015-05-19

    申请号：US14069198

    申请日：2013-10-31

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K3/356 ,  H03K3/037

    CPC classification number: H03K3/35625 ,  H03K3/356104

    Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

    Abstract translation: 描述了一种锁存器，其包括：第一AND-OR反相（AOI）逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源节点的相应的第一和第二保持器装置。 描述了一种触发器，其包括：第一锁存器，包括：第一AOI逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源的相应的第一和第二保持器装置，所述第一锁存器具有输出节点; 以及第二锁存器，其具有耦合到所述第一锁存器的输出节点的输入节点，所述第二锁存器具有输出节点以提供所述触发器的输出。

    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH
    9.
    发明公开
    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH 审中-公开

    公开(公告)号：US20240223167A1

    公开(公告)日：2024-07-04

    申请号：US18091970

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram K. Krishnamurthy

    IPC: H03K4/94 ,  H03K3/037

    CPC classification number: H03K4/94 ,  H03K3/037 ,  H03K19/20

    Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

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