中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.017 seconds)

    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator
    1.
    发明授权
    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator 有权

    公开(公告)号：US10928847B2

    公开(公告)日：2021-02-23

    申请号：US16147652

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy

    IPC: G06F9/02 ,  G06F1/06

    Abstract: Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.

    Hardware accelerators and methods for high-performance authenticated encryption
    2.
    发明授权
    Hardware accelerators and methods for high-performance authenticated encryption 有权

    公开(公告)号：US10705842B2

    公开(公告)日：2020-07-07

    申请号：US15943654

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy ,  Vinodh Gopal

    IPC: G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  H04L9/00 ,  H04L9/18 ,  G06F9/30 ,  G06F9/38 ,  H04L9/06

    Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

    Techniques for secure authentication
    3.
    发明授权
    Techniques for secure authentication 有权

    公开(公告)号：US10326596B2

    公开(公告)日：2019-06-18

    申请号：US15283315

    申请日：2016-10-01

    Applicant: INTEL CORPORATION

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: H04L9/00 ,  H04L9/32 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  H04L9/28

    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.

    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT
    5.
    发明申请
    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT 审中-公开

    公开(公告)号：US20200312404A1

    公开(公告)日：2020-10-01

    申请号：US16417538

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC: G11C11/419 ,  H04L9/32

    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION
    7.
    发明申请
    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION 审中-公开

    公开(公告)号：US20190305970A1

    公开(公告)日：2019-10-03

    申请号：US15942181

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/32 ,  H04L9/00

    Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

    Hybrid AES-SMS4 hardware accelerator
    9.
    发明授权
    Hybrid AES-SMS4 hardware accelerator 有权

    公开(公告)号：US10218497B2

    公开(公告)日：2019-02-26

    申请号：US15252741

    申请日：2016-08-31

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: G06F9/30 ,  G09C1/00 ,  H04L9/06

    Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.

    Device, system, and method to change a consistency of behavior by a cell circuit
    10.
    发明授权
    Device, system, and method to change a consistency of behavior by a cell circuit 有权

    公开(公告)号：US10825511B2

    公开(公告)日：2020-11-03

    申请号：US16417538

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC: G11C11/419 ,  H04L9/32 ,  G09G5/00 ,  G06F7/58

    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Patent Agency Ranking