公开(公告)号：US09710389B2

公开(公告)日：2017-07-18

申请号：US14643354

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC: G06F12/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

公开(公告)号：US10795681B2

公开(公告)日：2020-10-06

申请号：US14580603

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Sumit Ahuja

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.

公开(公告)号：US20210096866A1

公开(公告)日：2021-04-01

申请号：US17062556

申请日：2020-10-03

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Sumit Ahuja

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.

公开(公告)号：US12248785B2

公开(公告)日：2025-03-11

申请号：US17062556

申请日：2020-10-03

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Sumit Ahuja

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.