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公开(公告)号：US10437590B2
公开(公告)日：2019-10-08
申请号：US15719290
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Sofia Pediaditaki , Ethan Schuchman , Rangeen Basu Roy Chowdhury , Manjunath Shevgoor
IPC: G06F12/00 , G06F9/30 , G06F12/0846 , G06F12/128 , G06F9/52 , G06F12/0811
Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.
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公开(公告)号：US10324724B2
公开(公告)日：2019-06-18
申请号：US14971904
申请日：2015-12-16
Applicant: Intel Corporation
Inventor： Patrick P. Lai , Tyler N. Sondag , Sebastian Winkel , Polychronis Xekalakis , Ethan Schuchman , Jayesh Iyer
IPC: G06F9/30
Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.
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公开(公告)号：US09274799B1
公开(公告)日：2016-03-01
申请号：US14494829
申请日：2014-09-24
Applicant: Intel Corporation
Inventor： Sebastian Winkel , Ethan Schuchman , Tyler Sondag , Girish Venkatasubramanian
CPC classification number: G06F9/5038 , G06F9/30145 , G06F9/3836 , G06F9/3851 , G06F9/3877 , G06F9/4552
Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.
Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。
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4.发明授权Providing hardware support for shared virtual memory between local and remote physical memory 有权为本地和远程物理内存之间的共享虚拟内存提供硬件支持公开(公告)号：US09003164B2
公开(公告)日：2015-04-07
申请号：US14221741
申请日：2014-03-21
Applicant: Intel Corporation
Inventor： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
CPC classification number: G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程 记忆。 以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。 描述和要求保护其他实施例。
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公开(公告)号：US09858057B2
公开(公告)日：2018-01-02
申请号：US14956671
申请日：2015-12-02
Applicant: Intel Corporation
Inventor： Girish Venkatasubramanian , Chaitanya Mangla , Gerolf F. Hoflehner , Ethan Schuchman
CPC classification number: G06F8/447 , F01D5/082 , F02C7/18 , F05D2250/38 , F05D2260/14 , F05D2260/941 , G06F8/51 , G06F8/52 , G06F9/44589 , G06F9/4552 , G06F11/0751 , G06F11/30 , G06F11/3003 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , Y10T29/49 , Y10T29/49995
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160266905A1
公开(公告)日：2016-09-15
申请号：US14644130
申请日：2015-03-10
Applicant: Intel Corporation
Inventor： Sebastian Winkel , Ethan Schuchman , Rainer Theuer , Gregor Stellpflug , Tyler N. Sondag
CPC classification number: G06F9/3851 , G06F8/52 , G06F9/3017 , G06F9/4552 , G06F9/5027 , G06F2209/5018
Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.
Abstract translation: 将逻辑线程分配给物理线程的方法和装置。 在一个实施例中，一种装置包括数据存储装置，其存储当由硬件处理器执行时使得硬件处理器执行以下操作的代码：将指令转换为转换的指令，为翻译的指令分配逻辑线程， 线程图提示翻译指令; 以及硬件调度器，用于分配硬件处理器的物理线程以基于线程图提示来执行逻辑线程。
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7.发明授权Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode 有权用于指定和保存寄存器子集的单个指令，指定在唤醒后执行的工作监视功能的指针，以及进入低功耗模式公开(公告)号：US09164764B2
公开(公告)日：2015-10-20
申请号：US14286536
申请日：2014-05-23
Applicant: INTEL CORPORATION
Inventor： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
CPC classification number: G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US10409763B2
公开(公告)日：2019-09-10
申请号：US14319265
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Patrick P. Lai , Ethan Schuchman , David Keppel , Denis M. Khartikov , Polychronis Xekalakis , Joshua B. Fryman , Allan D. Knies , Naveen Neelakantam , Gregor Stellpflug , John H. Kelm , Mirem Hyuseinova Seidahmedova , Demos Pavlou , Jaroslaw Topp
Abstract: Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
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9.发明授权公开(公告)号：US09996356B2
公开(公告)日：2018-06-12
申请号：US14998299
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Oleg Margulis , Jason M. Agron , Ethan Schuchman , Sebastian Winkel , Youfeng Wu , Gisle Dankel
CPC classification number: G06F9/30185 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/3865
Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.
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10.发明授权Methods and apparatus to validate translated guest code in a dynamic binary translator 有权在动态二进制翻译器中验证翻译的访客代码的方法和装置公开(公告)号：US09223553B2
公开(公告)日：2015-12-29
申请号：US14125263
申请日：2013-09-26
Applicant: INTEL CORPORATION
Inventor： Girish Venkatasubramanian , Chaitanya Mangla , Gerolf F. Hoflehner , Ethan Schuchman
CPC classification number: G06F8/447 , F01D5/082 , F02C7/18 , F05D2250/38 , F05D2260/14 , F05D2260/941 , G06F8/51 , G06F8/52 , G06F9/44589 , G06F9/4552 , G06F11/0751 , G06F11/30 , G06F11/3003 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , Y10T29/49 , Y10T29/49995
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.
Abstract translation: 公开了方法，装置，系统和制品，以在动态二进制转换器中验证翻译的客户代码。 本文公开的示例设备包括翻译器，用于生成在主机上执行的代码的第一翻译，客户代码的第一次翻译以便于创建第一翻译的客户代码，以及翻译器以生成所翻译的客人的第二翻译 在主机上执行的代码。 该示例设备还包括翻译版本管理器，用于基于执行第一翻译的一部分来识别第一主机状态，以及翻译版本管理器，用于基于执行第二翻译的一部分来识别第二主机状态。 该示例系统还包括基于第一主机状态和第二主机状态之间的比较来确定第二转换的状态发散状态的验证器。
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