公开(公告)号：US09712898B2

公开(公告)日：2017-07-18

申请号：US14469243

申请日：2014-08-26

Applicant: Intel Corporation

Inventor： Terrence Trausch ,  Gabriel C. Cox ,  James T. Langston, Jr. ,  Guy L. Williams

IPC: G02B6/38 ,  G02B6/44 ,  H04Q11/00 ,  H04Q1/02

CPC classification number: H04Q11/0003 ,  G02B6/3897 ,  G02B6/4452 ,  H04Q1/09

Abstract: Embodiments of the present disclosure provide arrangements for aggregating network traffic of compute nodes of various computing sleds of computing trays of a computing rack assembly in a data center. In one embodiment, a computing rack assembly may include a plurality of computing trays. A computing tray may removably include a number of sleds. Each sled may include a number of compute nodes. The computing tray may further include an optical network aggregation component to aggregate network traffic of the compute nodes of various sleds of a computing tray. Other embodiments may be described and/or claimed.

公开(公告)号：US09529583B2

公开(公告)日：2016-12-27

申请号：US14142687

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Christopher Neil Bradley ,  Terrence Trausch

IPC: H04L29/08 ,  G06F9/445

CPC classification number: G06F8/654 ,  G06F8/65 ,  H04L67/1044

Abstract: An apparatus for compute module management is described herein. The apparatus includes a host system and a logic solution. The host system includes a central processing unit and a plurality of sensors that collect system management data from multiple interfaces. The logic solution consolidates the system management data to a single format for a single interface and transmits the system management data to a central authority. The central authority includes system management firmware for managing each compute module using the consolidated system management data.

Abstract translation: 本文描述了一种用于计算模块管理的装置。 该装置包括主机系统和逻辑解决方案。 主机系统包括中央处理单元和从多个接口收集系统管理数据的多个传感器。 逻辑解决方案将系统管理数据整合为单个接口的单一格式，并将系统管理数据传输到中央机构。 中央机构包括使用统一的系统管理数据管理每个计算模块的系统管理固件。

公开(公告)号：US10515032B2

公开(公告)日：2019-12-24

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/14 ,  G06F13/40 ,  G06F13/42

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.

公开(公告)号：US10346156B2

公开(公告)日：2019-07-09

申请号：US15386057

申请日：2016-12-21

Applicant: INTEL CORPORATION

Inventor： Christopher Neil Bradley ,  Terrence Trausch

IPC: G06F13/40 ,  G06F8/654 ,  G06F8/65 ,  H04L29/08

Abstract: An apparatus for compute module management is described herein. The apparatus includes a host system and a logic solution. The host system includes a central processing unit and a plurality of sensors that collect system management data from multiple interfaces. The logic solution consolidates the system management data to a single format for a single interface and transmits the system management data to a central authority. The central authority includes system management firmware for managing each compute module using the consolidated system management data.

公开(公告)号：US20190138470A1

公开(公告)日：2019-05-09

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.