公开(公告)号：US20210209052A1

公开(公告)日：2021-07-08

申请号：US17041519

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

IPC: G06F13/40 ,  G06F9/4401

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

公开(公告)号：US11327918B2

公开(公告)日：2022-05-10

申请号：US17041519

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

IPC: G06F13/40 ,  G06F9/4401 ,  G06F11/20

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

公开(公告)号：US11782645B2

公开(公告)日：2023-10-10

申请号：US17568956

申请日：2022-01-05

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

公开(公告)号：US11288010B2

公开(公告)日：2022-03-29

申请号：US16638694

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.