公开(公告)号：US12217101B2

公开(公告)日：2025-02-04

申请号：US18309650

申请日：2023-04-28

Applicant: INTEL CORPORATION

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US11675630B2

公开(公告)日：2023-06-13

申请号：US16541979

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06F9/5083 ,  G06F16/9024 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US20240419956A1

公开(公告)日：2024-12-19

申请号：US18749806

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230333913A1

公开(公告)日：2023-10-19

申请号：US18309650

申请日：2023-04-28

Applicant: INTEL CORPORATION

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06F9/5083 ,  G06F16/9024 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US20180314934A1

公开(公告)日：2018-11-01

申请号：US15499900

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsh ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220066923A1

公开(公告)日：2022-03-03

申请号：US17523384

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Zigi Walter ,  Roni Rosner ,  Michael Behar

IPC: G06F12/02 ,  G06F12/06 ,  G06F9/30 ,  G06F15/78 ,  G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines runtime memory requirements of an artificial intelligence (AI) application, defines a remote address range for a plurality of memories based on the runtime memory requirements, wherein each memory in the plurality of memories corresponds to a processor in a plurality of processors, and defines a shared address range for the plurality of memories based on the runtime memory requirements, wherein the shared address range is aliased. In one example, the technology configures memory mapping hardware to access the remote address range in a linear sequence and access the shared address range in a hashed sequence.

公开(公告)号：US11151074B2

公开(公告)日：2021-10-19

申请号：US16542085

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Roni Rosner ,  Ravi Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Henrietta Bezbroz ,  Alexander Gendler ,  Ohad Falik ,  Zigi Walter ,  Michael Behar ,  Shlomi Alkalay

IPC: G06F13/42 ,  G06N3/04 ,  G06F13/20 ,  G06F12/0893

Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

公开(公告)号：US11036277B2

公开(公告)日：2021-06-15

申请号：US16541674

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Avital Paz ,  Eran Nevet ,  Zigi Walter

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3234

Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.

公开(公告)号：US12033063B2

公开(公告)日：2024-07-09

申请号：US18174275

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/06 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US11847497B2

公开(公告)日：2023-12-19

申请号：US17561500

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/46 ,  G06F9/50 ,  G06F3/06

CPC classification number: G06F9/5016 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/505

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.