公开(公告)号：US3836719A

公开(公告)日：1974-09-17

申请号：US37609573

申请日：1973-07-02

Applicant: ITT

Inventor： CLARK J

IPC: H04J3/17 ,  H04J3/24 ,  H04J5/00

CPC classification number: H04J3/24 ,  H04J3/17

Abstract: A TASI communication system includes P input PCM speech channels to a transmitter and P output PCM speech channels from a receiver and T PCM channels for T of the P channels to be propagated between the transmitter and the receiver, where P is an integer greater than one and T is an integer greater than one but less than P. P PCM speech words corresponding to the P input and output channels are arranged to form a first TDM frame format and T speech words corresponding to the T channels and one-half of a control word are organized to form a second TDM frame format with 2(T + 1) frames of the second format being organized to form a multiframe. The first (2(T + 1) -2) frames of the second frame format in the multiframe includes a different one of transmitted assignment code words for each of the first T of the control words. An assignment control arrangement is provided at both the transmitter and the receiver. The transmitter assignment control arrangement includes a storage means to store in sequence code words identifying the previous assignment for each of the P channels. Logic circuitry is provided responsive to a first transmit timing signal identifying each of the P speech words in sequence in the first format, a second transmit timing signal identifying each of the T speech words in sequence in the second format, a third transmit timing signal identifying each of the T control words in sequence during each search cycle, a fourth transmit timing signal identifying each of the T control words in sequence during each update cycle at the transmitter and the code words at the output of the storage means to determine the connection and activity status of each of the P channels and to produce code words identifying the assignment of previously connected ones or active ones of the P channels to particular ones of the T channels that are still connected and active and to identify new assignments to enable newly active ones of the P channels to be connected to available ones of the T channels and second logic circuitry responsive to at least the code words at the output of the storage means, the first and fourth transmit timing signals to return the code words to the storage means identifying previously established assignments (previous connections) that are to remain as before and to update the code words stored in the storage means for any new assignments. The receiver assignment control arrangement also includes a storage means to store in sequence code words identifying the previous assignment for each of the P channels as received from the transmitter and third logic circuitry responsive to transmitted code words, a first receive timing signal identifying each of the P speech words in sequence in the first format, a second receive timing signal identifying each of the T speech words in sequence in the second format, a third timing signal identifying each of the T control words in sequence during each update cycle at the receiver and the code words at the output of the receiver storage means to return the code words to the receiver storage means identifying previously established connections that are to remain and to update the code words stored in the receiver storage means for the new assignments.

公开(公告)号：US3840708A

公开(公告)日：1974-10-08

申请号：US37768673

申请日：1973-07-09

Applicant: ITT

Inventor： CLARK J

IPC: H04J3/14 ,  H04J3/17

CPC classification number: H04J3/17 ,  H04J3/14

Abstract: There is disclosed an arrangement to test a TASI communication system including a speech activity simulator coupled to the assignment control arrangement and between the output of the speech detector and the input of the status memory so that the activity simulator time shares the status memory with the speech detector and couples a control signal to the assignment control arrangement indicating active speech channels with the control signal being produced by either the speech detector or the activity simulator. The activity simulator can be operated only when a binary 0 condition for both the eighth and ninth bits of a 9-bit code word from the speech detector for each input speech channel is detected. The activity simulator is capable of providing four different modes of simulation as determined by two front panel mode switches and a random activity method selecting switch. When the two mode switches provide predetermined binary conditions other than 00, which indicates normal speech detector activity, a simulated steady activity, a simulated steady inactivity or a simulated random activity can be provided. When the mode switches provide a selected binary condition indicating simulated random activity, the random activity switch can select either of two simulated random activities.

公开(公告)号：US3754102A

公开(公告)日：1973-08-21

申请号：US3754102D

申请日：1972-05-10

Applicant: ITT

Inventor： CLARK J

IPC: H04J3/06

CPC classification number: H04J3/0605

Abstract: Frame synchronization for a binary data signal including a superframe having M midframes, each of the M midframes, including m subframes is accomplished by providing within the data signal a first sync signal having a first predetermined pattern disposed in each of the M midframes and a second sync signal having a second predetermined pattern different than the first pattern composed of M bits, each of the M bits being disposed in a different one of the M midframes, wherein M and m are integers greater than 1, such as M 64 and m 15. A data bit rate clock is extracted from the data signal and applied to a cascade connection of digital dividers to provide local timing, including subframe rate timing signals, midframe rate timing signals, superframe rate timing signals, and a locally generated first sync signal. A typical arrangement of a six stage shift register (where M is typically equal to 64) and feedback logic generates locally the second sync signal. A first digital comparator compares the locally generated first sync signal with the first sync signal contained in the data signal and the resulting matches and mismatches are integrated in a digital integrator, such as an up-down counter. When the count of the digital integrator is below a predetermined count threshold and a mismatch is present at a time defining when the first sync signal contained in the data signal should occur relative to the local timing, a HALT signal is produced which inhibits the flow of bit rate clock pulses to the first counter of the cascade connected counters (dividers) so as to control the phase of the timing signals with respect to the data signal to establish and maintain synchronization of the local timing to the midframes of the data signal. The received second sync signal and the locally generated second sync signal are compared a bit at a time in a digital comparator, which produce as the result of bit errors in the received second sync signal or as the result of incorrect phase of the locally generated second sync signal matches and mismatches which also are applied to the digital integrating updown counter. When the count of the digital integrator is less than a second count threshold different than the first threshold, switching logic connects the received second sync signal to the shift register to provide therein error free bits of a portion of the received second sync signal which through the cooperation of the feedback logic generates an error free locally generated second sync signal so that in cooperation with synchronization of the midframe, the superframe is synchronized.

公开(公告)号：US3832493A

公开(公告)日：1974-08-27

申请号：US37119173

申请日：1973-06-18

Applicant: ITT

Inventor： CLARK J

IPC: H04J3/17 ,  H04J5/00

CPC classification number: H04J3/175

Abstract: This relates to a digital speech detector applicable to a TASI communication system wherein the detector detects the presence or absence of speech in a plurality of digital code groups each of which indicate a quantized amplitude of a speech sample. The speech detector is divided into two portions. The first portion is an instantaneous detector that detects the quantized amplitude of each of the code groups in sequence and produces an up count signal when the detected quantized amplitude is greater than a first threshold value or less than a second threshold value less than the first threshold value and produces a down count signal when the detected quantized amplitude is between the first and second threshold values. The second portion includes an integrating counting circuit which integrates the up and down count signals and produces a resultant value of integration. The counting circuit produces a second output signal indicating speech activity in the code groups when the value of integration is above a third threshold value and produces a second output signal indicating an absence of speech activity in the code groups when the value of integration is below the third threshold value. The counting circuit has three different counting rates. The greatest counting rate occurs between a minimum count level and the third threshold value until the third threshold value is reached. An intermediate counting rate occurs between the third threshold value after it has been reached and a maximum count level until the maximum count level is reached. The smallest counting rate occurs between the maximum count level after it has been reached and the minimum count level until the minimum count level is reached again. The first output signal from the counting circuit is the signal that controls the assignment of those PCM code groups having speech activity to a particular one of the TASI channels transmitted from the transmitting portion of the TASI communication system.

Abstract translation: 这涉及适用于TASI通信系统的数字语音检测器，其中检测器检测多个数字代码组中是否存在语音，每个数字代码组都表示语音样本的量化幅度。 语音检测器被分成两部分。 第一部分是瞬时检测器，其依次检测每个代码组的量化幅度，并且当检测到的量化幅度大于第一阈值或小于小于第一阈值的第二阈值时产生向上计数信号 并且当检测到的量化幅度在第一和第二阈值之间时产生递减计数信号。 第二部分包括积分计数电路，其对上和下计数信号进行积分并产生合成的积分值。 当积分值高于第三阈值时，计数电路产生指示代码组中的语音活动的第二输出信号，并且当积分值低于第三阈值时产生指示代码组中没有语音活动的第二输出信号 第三阈值。 计数电路有三种不同的计数率。 最大计数率发生在最小计数级别和第三阈值之间，直到达到第三阈值。 在到达第三阈值之后发生中间计数率，直到达到最大计数级别为止的最大计数级别。 在达到最大计数水平和最小计数水平直到再次达到最小计数水平之间发生最小计数率。 来自计数电路的第一输出信号是控制具有语音活动的那些PCM码组的分配到从TASI通信系统的发送部分发送的TASI信道中的特定一个信道的信号。

公开(公告)号：US3789307A

公开(公告)日：1974-01-29

申请号：US3789307D

申请日：1971-09-20

Applicant: ITT

Inventor： CLARK J

IPC: H03L7/00 ,  H04J3/06 ,  H03B3/04

CPC classification number: H03L7/00 ,  H04J3/06

Abstract: There is disclosed a framing control circuit for a frame synchronization system. The circuit includes a sense circuit having a first integrator with a relatively long time constant and a first amplitude comparator to detect an out-ofsynchronization condition, and a search circuit having a second integrator with a relativeyly short time constant, a second amplitude comparator and a third amplitude comparator to detect an in-synchronization condition. The third amplitude comparator produces a high output and a mode flip flop having its ''''1'''' input coupled to the first comparator produces a high output on its ''''1'''' output when an out-of-synchronization condition is present. The simultaneous presence of these two signals activates the search logic of the frame synchronization system. The ''''0'''' input of the flip flop is coupled to the second comparator and produces a high output on its ''''0'''' output when an insynchronization condition is present. A diode is coupled between the ''''0'''' output of the flip flop and the input of the first integrator, said diode being rendered conductive when the ''''0'''' output is low. This diode conduction will reset the first ingegrator to a reference operating level which ensures full use of the time constant thereof and, hence, better protection against accidental phase shift (loss of synchronization) due to a short fade.

Abstract translation: 公开了一种用于帧同步系统的成帧控制电路。 该电路包括具有相对较长时间常数的第一积分器和检测失步条件的第一幅度比较器的检测电路，以及具有相对较短时间常数的第二积分器的搜索电路，第二幅度比较器 以及第三幅度比较器，用于检测同步状态。 第三幅度比较器产生高输出，并且模式触发器具有耦合到第一比较器的“1”输入，当存在失步条件时，在其“1”输出上产生高输出。 这两个信号的同时存在激活了帧同步系统的搜索逻辑。 触发器的“0”输入耦合到第二比较器，并且当存在同步状态时，在其“0”输出上产生高输出。 二极管耦合在触发器的“0”输出和第一积分器的输入之间，当“0”输出为低时，所述二极管导通。 该二极管导通将使第一个起动器复位到参考工作电平，从而确保充分利用其时间常数，并因此更好地防止由于短时间褪色引起的意外相移（失去同步）。

公开(公告)号：US3742145A

公开(公告)日：1973-06-26

申请号：US3742145D

申请日：1972-04-17

Applicant: ITT

Inventor： CLARK J ,  HAUSSMANN R

IPC: H04J3/07 ,  H04J3/04

CPC classification number: H04J3/073

Abstract: There is described an asynchronous multiplexer and demultiplexer that operates on the basis of a stuff only technique. The multiplexer includes a different elastic store for each of the asynchronous input PCM data groups. Each of the elastic stores include a buffer register whose writing clock is synchronous with the asynchronous group input bit rate clock and a read clock which is synchronous with the bit rate of a synchronous data format employed for multiplexing the asynchronous group inputs. Each of the elastic stores produce a stuff request signal when the phase difference of the read and write clocks is equal to a given period, in numbers of bit periods. A common stuff control circuit samples the stuff requests and provides a control signal to inhibit the read clock to add or stuff a single stuff bit to the associated group data for each stuff request. Timing signals generated from a reference oscillator define the synchronous data format which includes 64 midframes within a superframe with each of the midframes including 15 subframes. Odd numbered ones of the subframes include 9 data bits and even numbered ones of the subframes include 8 data bits. The 9th data bit of the odd numbered subframes provide an overhead channel for transmitting digital voice orderwire, digital data orderwire, control words, a ''''zero'''' short sync bit, a ''''one'''' short sync bit and a long sync bit in each midframe. The bit assigned to the control words are employed to identify at the demultiplexer where the stuff bit has been added to the data format. The demultiplexer includes timing signal generators driven by the superframe rate recovered from the received data signal to provide the necessary timing signals to identify the supergroup frame, the midframe, the subframes and the data bits within the subframes. The timing signal generator in the demultiplexer is synchronized to the timing signal generators defining the data format in the multiplexer by a superframe recovery circuit responsive to both a short sync code and a pseudo-random long sync code. A common destuffing control is provided responsive to the code word identifying the presence or absence of a stuff bit to destuff the identified group data and thereby return the stuffed multiplexed group data to asynchronous group data as originally applied to the elastic stores of the multiplexer. The demultiplex includes for each asynchronous group data a different elastic store wherein the write clock is controlled by the recovered supergroup bit rate and the read clock is controlled at the group or midframe rate provided by the timing signal generators. The destuff control from the common destuff control circuit controls the write counter to cause destuffing of the associated one of the stuffed group data. A heterodyne type phase locked loop is employed in conjunction with each of the elastic stores to remove jitter from the destuffed group data.

公开(公告)号：US3735045A

公开(公告)日：1973-05-22

申请号：US3735045D

申请日：1970-08-24

Applicant: ITT CORP NUTLEY

Inventor： CLARK J

IPC: H04J3/06 ,  H04L7/08

CPC classification number: H04J3/06

Abstract: A framing control circuit for a frame synchronization system employing one integrator for both the sense and search modes rather than a separate integrator for each of the sense and search modes. A voltage controlled amplitude control circuit is disposed at the input to the integrator. The control signal for the control circuit is produced by a bistable device coupled to the output of the integrator. A low binary control signal, indicating a sense mode, provides a relatively low amplitude input signal to the integrator and, hence, an effective long time constant for the integrator. A high binary control signal, indicating a search mode, provides a relatively large amplitude input signal to the integrator and, hence, an effective short time constant for the integrator.

Abstract translation: 用于帧同步系统的成帧控制电路，其对于感测和搜索模式都采用一个积分器，而不是针对每个感测和搜索模式的单独的积分器。 压控幅度控制电路设置在积分器的输入端。 用于控制电路的控制信号由耦合到积分器的输出的双稳态器件产生。 指示感测模式的低二进制控制信号向积分器提供相对较低的振幅输入信号，因此为积分器提供有效的长时间常数。 指示搜索模式的高二进制控制信号向积分器提供相对较大的幅度输入信号，因此为积分器提供有效的短时间常数。