公开(公告)号：US09129805B2

公开(公告)日：2015-09-08

申请号：US13910080

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L21/8234 ,  H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract translation: ESD保护器件包括具有源极区，漏极区和栅极区的MOS晶体管。 指定用于ESD保护的节点电耦合到漏极。 二极管耦合在栅极和源极之间，其中如果MOS晶体管处于有源工作区域，二极管将被反向偏置。

公开(公告)号：US20150229126A1

公开(公告)日：2015-08-13

申请号：US14690739

申请日：2015-04-20

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Wolfgang Soldner ,  Cornelius Christian Russ ,  David Alvarez ,  Adrien Ille

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H01L29/0692 ,  H01L29/1083

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Abstract translation: 在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件 。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器 。

公开(公告)号：US20190260203A1

公开(公告)日：2019-08-22

申请号：US15902216

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Stefan Seidl ,  David Alvarez

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.

公开(公告)号：US09478979B2

公开(公告)日：2016-10-25

申请号：US14690739

申请日：2015-04-20

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Wolfgang Soldner ,  Cornelius Christian Russ ,  David Alvarez ,  Adrien Ille

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H01L29/0692 ,  H01L29/1083

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

公开(公告)号：US20130264646A1

公开(公告)日：2013-10-10

申请号：US13910080

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US20130264645A1

公开(公告)日：2013-10-10

申请号：US13910071

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract translation: ESD保护器件包括具有源极区，漏极区和栅极区的MOS晶体管。 指定用于ESD保护的节点电耦合到漏极。 二极管耦合在栅极和源极之间，其中如果MOS晶体管处于有源工作区域，二极管将被反向偏置。

公开(公告)号：US10749338B2

公开(公告)日：2020-08-18

申请号：US15902216

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Stefan Seidl ,  David Alvarez

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02 ,  H01L27/06 ,  H02M3/07

Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.

公开(公告)号：US09859270B2

公开(公告)日：2018-01-02

申请号：US14831024

申请日：2015-08-20

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/04 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US20160071833A1

公开(公告)日：2016-03-10

申请号：US14942589

申请日：2015-11-16

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US09263428B2

公开(公告)日：2016-02-16

申请号：US13910071

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L23/62 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.