公开(公告)号：US09859270B2

公开(公告)日：2018-01-02

申请号：US14831024

申请日：2015-08-20

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/04 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US20160071833A1

公开(公告)日：2016-03-10

申请号：US14942589

申请日：2015-11-16

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US09263428B2

公开(公告)日：2016-02-16

申请号：US13910071

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L23/62 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

公开(公告)号：US20150357322A1

公开(公告)日：2015-12-10

申请号：US14831024

申请日：2015-08-20

Applicant: Infineon Technologies AG

Inventor： Cornelius Christian Russ ,  David Alvarez

IPC: H01L27/02 ,  H01L29/04 ,  H01L29/417 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/8234 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/04 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/66136 ,  H01L29/66568

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract translation: ESD保护器件包括具有源极区，漏极区和栅极区的MOS晶体管。 指定用于ESD保护的节点电耦合到漏极。 二极管耦合在栅极和源极之间，其中如果MOS晶体管处于有源工作区域，二极管将被反向偏置。

公开(公告)号：US09087892B2

公开(公告)日：2015-07-21

申请号：US14028403

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract translation: 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。

公开(公告)号：US09478979B2

公开(公告)日：2016-10-25

申请号：US14690739

申请日：2015-04-20

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Wolfgang Soldner ,  Cornelius Christian Russ ,  David Alvarez ,  Adrien Ille

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H01L29/0692 ,  H01L29/1083

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

公开(公告)号：US09455275B2

公开(公告)日：2016-09-27

申请号：US14168978

申请日：2014-01-30

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Maryam Shojaei Baghini ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L27/12 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L27/1211 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/78624

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract translation: 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。

公开(公告)号：US09263430B2

公开(公告)日：2016-02-16

申请号：US14606861

申请日：2015-01-27

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius Christian Russ ,  Kai Esmark

IPC: H01L27/00 ,  H01L27/02 ,  H01L29/74 ,  H01L21/82

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

公开(公告)号：US20150340442A1

公开(公告)日：2015-11-26

申请号：US14743796

申请日：2015-06-18

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/267 ,  H01L29/45 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract translation: 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。

公开(公告)号：US20150144996A1

公开(公告)日：2015-05-28

申请号：US14606861

申请日：2015-01-27

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius Christian Russ ,  Kai Esmark

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.