公开(公告)号：US20240006873A1

公开(公告)日：2024-01-04

申请号：US17852530

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Navneet Kumar Singh ,  Shailendra Singh Chauhan ,  Aiswarya Pious ,  Amarjeet Kumar ,  Samarth Alva

IPC: H02H5/00 ,  H01R13/66

CPC classification number: H02H5/00 ,  H01R13/6683 ,  H01R24/60

Abstract: Systems, apparatuses and methods may provide for power adapter technology that includes an adapter plug having a housing, a plurality of contacts positioned within the housing, wherein the plurality of contacts includes one or more configuration channel contacts, and a piezoelectric membrane positioned on an external surface of the housing, wherein the piezoelectric membrane is electrically connected to the one or more configuration channel contacts. Additionally, sink device technology may detect a signal from the piezoelectric membrane of the adapter plug via the configuration channel contact(s), wherein the signal indicates user contact with the adapter plug, and disconnect a bulk capacitor from a receptacle adjacent to the adapter plug in response to a disconnect condition associated with the user contact.

公开(公告)号：US20230198568A1

公开(公告)日：2023-06-22

申请号：US17559843

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Maruti Tamrakar ,  Jayprakash Thakur ,  Sagar Gupta ,  Rajasekar Arumanayagam ,  Amarjeet Kumar

IPC: H04B1/44

CPC classification number: H04B1/44

Abstract: Embodiments of the present disclosure are directed to antenna switching systems. For example, some embodiments may include a switching system to allow a computing system to switch between an internal antenna and an external antenna. Other embodiments may be described and claimed.

公开(公告)号：US12025971B2

公开(公告)日：2024-07-02

申请号：US17667551

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Navneet Singh ,  Samarth Alva ,  Amarjeet Kumar ,  Gaurav Hada

IPC: G05B19/4155 ,  H01L23/373 ,  H01L23/538 ,  H01R12/70 ,  H05K1/18

CPC classification number: G05B19/4155 ,  H01L23/3736 ,  H01L23/538 ,  H01R12/70 ,  G05B2219/40269 ,  G05B2219/45031 ,  H05K1/181 ,  H05K2201/10378

Abstract: An apparatus includes a memory interposer including a socket including an inner surface, one or more memories disposed on the inner surface, a bottom surface opposite to the inner surface, and pogo pins disposed on the bottom surface and respectively corresponding to the one or more memories, the pogo pins being configured to connect the one or more memories to a printed circuit board (PCB) including a semiconductor die. The apparatus further includes an intermediate thermal head attached to the memory interposer. The memory interposer is movable with respect to the intermediate thermal head.

公开(公告)号：US12300918B2

公开(公告)日：2025-05-13

申请号：US17479596

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Navneet Kumar Singh ,  Aiswarya M. Pious ,  Richard S. Perry ,  Amarjeet Kumar ,  Siva Prasad Jangili Ganga ,  Gaurav Hada ,  Sushil Padmanabhan ,  Konika Ganguly

IPC: H01R12/00 ,  H01R12/70 ,  H01R12/73 ,  H01R43/26

Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.