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公开(公告)号：US20240129149A1
公开(公告)日：2024-04-18
申请号：US18397668
申请日：2023-12-27
Applicant: Intel Corporation
Inventor： Aiswarya M. Pious , Tao Tao , Stanley Jacob Baran , Michael Daniel Rosenzweig , Chia-Hung Sophia Kuo , Rahul R , Nagalakshmi S , Praveen Kashyap Ananta Bhat , Balvinder Pal Singh , Navya P , Jason Tanner , Passant V. Karunaratne , Venkateshan Udhayan , Srikanth Potluri
IPC: H04L12/18 , G06F3/04817 , H04L51/04 , H04L65/1069 , H04L65/80
CPC classification number: H04L12/1831 , G06F3/04817 , H04L51/04 , H04L65/1069 , H04L65/80
Abstract: An example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. The disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. The disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. The disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.
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公开(公告)号：US20210153340A1
公开(公告)日：2021-05-20
申请号：US17127407
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Jaejin Lee , James Panakkal , Min Suet Lim , Aiswarya M. Pious
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.
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公开(公告)号：US12300918B2
公开(公告)日：2025-05-13
申请号：US17479596
申请日：2021-09-20
Applicant: Intel Corporation
Inventor： Navneet Kumar Singh , Aiswarya M. Pious , Richard S. Perry , Amarjeet Kumar , Siva Prasad Jangili Ganga , Gaurav Hada , Sushil Padmanabhan , Konika Ganguly
Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.
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公开(公告)号：US12106818B2
公开(公告)日：2024-10-01
申请号：US17133484
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Aiswarya M. Pious , Raji James , Phani K. Alaparthi , George Vergis , Bill Nale , Konika Ganguly
IPC: G11C5/14 , G06F1/3225 , G06F1/3228 , G06F1/3234 , G06F1/3296 , G11C11/4074
CPC classification number: G11C5/148 , G06F1/3225 , G06F1/3228 , G06F1/3243 , G06F1/3296 , G11C5/141 , G11C5/147 , G11C11/4074 , G11C2207/2227
Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
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Patent Agency Ranking
公开(公告)号：US20240334715A1
公开(公告)日：2024-10-03
申请号：US18126833
申请日：2023-03-27
Applicant: Intel Corporation
Inventor： Navneet Kumar Singh , Phani Alaparthi , Samarth Alva , Ritu Bawa , Gaurav Hada , Aiswarya M. Pious
CPC classification number: H10B80/00 , H01L23/315 , H01L23/481 , H01L24/32 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/32225 , H01L2225/06572
Abstract: Technologies for memory on package with reduced package thickness are disclosed. In the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. The die assembly is mounted on another substrate, such as a mainboard. A cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. Positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.
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公开(公告)号：US20220095456A1
公开(公告)日：2022-03-24
申请号：US17543311
申请日：2021-12-06
Applicant: Intel Corporation
Inventor： Arumanayagam Rajasekar , Tin Poay Chuah , Sushil Padmanabhan , Aiswarya M. Pious , Navneet Kumar Singh
Abstract: In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.
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公开(公告)号：US12167530B2
公开(公告)日：2024-12-10
申请号：US17127407
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Jaejin Lee , James Panakkal , Min Suet Lim , Aiswarya M. Pious
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.
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公开(公告)号：US20240406622A1
公开(公告)日：2024-12-05
申请号：US18204856
申请日：2023-06-01
Applicant: Intel Corporation
Inventor： Jaison Fernandez , Adam Kupryjanow , Srikanth Potluri , Tarakesava Reddy Koki , Aiswarya M. Pious
Abstract: A computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. The audio signals are associated with audio emitted from a same source. The method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.
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公开(公告)号：US20190052111A1
公开(公告)日：2019-02-14
申请号：US15571626
申请日：2016-11-16
Applicant: Intel Corporation
Inventor： Jr-Wei Wu , Chetan Verma , Aiswarya M. Pious
Abstract: System and techniques for wireless charging of a portable virtual reality (VR) host system are described herein. The present subject matter provides various examples to power a portable VR host system that allows for free movement by the user. In various embodiments the present subject matter provides connections on the footwear of the user that supply electrical power to a VR host worn by the user. In various examples, a connection technology is employed to provide connections between the user wearing the VR host system and conductive mats, plates, or flooring that are powered to provide electrical power to the VR host system via connections to the user's apparel when standing. Other forms of connection technology may be employed, such as inductive wireless technology or radio frequency signal technology that uses wireless power coils or antennae to receive power and provide it to the VR host worn by the user.
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