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公开(公告)号：US12131985B2
公开(公告)日：2024-10-29
申请号：US17470519
申请日：2021-09-09
Applicant: CORNING INCORPORATED
Inventor： Mandakini Kanungo , Prantik Mazumder , Chukwudi Azubuike Okoro , Ah-Young Park , Scott Christopher Pollard , Rajesh Vaddi
IPC: C25D3/38 , C03C3/06 , C03C15/00 , C03C17/06 , C03C17/10 , C03C23/00 , C23C14/18 , C23C18/38 , C23C28/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/48 , H01L23/498 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/38 , C03C3/076 , C25D7/12 , H01L23/00 , H01L23/492 , H05K3/00 , H05K3/42
CPC classification number: H01L23/49827 , C03C3/06 , C03C15/00 , C03C17/06 , C03C17/10 , C03C23/0025 , C23C14/18 , C23C18/38 , C23C28/02 , H01L21/76877 , H01L23/15 , H01L23/481 , H01L23/49838 , H05K1/0271 , H05K1/0306 , H05K1/115 , H05K3/388 , C03C3/076 , C03C2218/115 , C25D3/38 , C25D7/123 , H01L21/486 , H01L23/4924 , H01L23/49866 , H01L23/564 , H05K3/002 , H05K3/0029 , H05K3/0055 , H05K3/423 , H05K3/425 , H05K3/428 , H05K2201/068 , H05K2201/09545 , H05K2201/09563 , H05K2201/09609 , H05K2201/09827 , H05K2201/09854 , H05K2201/0989 , H05K2201/10378 , H05K2203/1194 , H05K2203/1361 , H05K2203/143 , H05K2203/1438 , H05K2203/162 , Y10T428/24273 , Y10T428/24479 , Y10T428/24851 , Y10T428/24917 , Y10T428/24926
Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.
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公开(公告)号：US20240357746A1
公开(公告)日：2024-10-24
申请号：US18326031
申请日：2023-05-31
Applicant: INNODISK CORPORATION
Inventor： CHIH-CHIEH KAO
IPC: H05K1/18
CPC classification number: H05K1/181 , H05K1/182 , H05K1/189 , H05K2201/09072 , H05K2201/10015 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , H05K2201/10545 , H05K2201/10628
Abstract: A high capacitance module for electrically connecting to a second circuit board comprises a first circuit board provided with a plurality of metal contacts and at least one capacitor core arranged on the first circuit board. The capacitor cores have connection pins that are electrically connected to the metal contacts through conductive glue. An adhesive layer covers the capacitor cores. The capacitor cores are electrically connected to a memory module arranged on the second circuit board.
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公开(公告)号：US20240334608A1
公开(公告)日：2024-10-03
申请号：US18740889
申请日：2024-06-12
Inventor： Chia-Kuei HSU , Ming-Chih YEW , Po-Chen LAI , Po-Yao LIN , Shin-Puu JENG
IPC: H05K1/18 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065 , H05K3/28 , H05K3/34
CPC classification number: H05K1/181 , H01L25/0655 , H05K3/284 , H01L23/3185 , H01L23/49811 , H01L23/5383 , H01L24/73 , H01L24/92 , H01L24/97 , H01L2224/73204 , H01L2224/92125 , H01L2224/95001 , H05K3/3436 , H05K2201/10378 , H05K2201/10727 , H05K2201/10734 , H05K2201/10977 , H05K2203/107
Abstract: A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.
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4.发明公开公开(公告)号：US20240297093A1
公开(公告)日：2024-09-05
申请号：US18645678
申请日：2024-04-25
Applicant: Vitesco Technologies GmbH
Inventor： Detlev Bagung , Christina Quest-Matt , Thomas Riepl , Daniela Wolf
IPC: H01L23/373 , H01L23/495 , H01L23/498 , H05K1/18 , H05K3/34
CPC classification number: H01L23/3735 , H01L23/49838 , H05K3/341 , H01L23/49562 , H05K1/181 , H05K2201/10166 , H05K2201/10378
Abstract: A heat dissipation device for soldering onto a printed circuit board for a semiconductor component arrangement. The device includes a semiconductor component a first electrical connector and at least one further electrical connector and a prefabricated metal block group. The metal block group has a first metal block arranged between the semiconductor component and the printed circuit board, connected to a first electrical connector of the semiconductor component by a solder joint and connected to at least one conductor track of the printed circuit board by a further solder joint. The metal block group includes at least one further metal block interposed between the further electrical connection and the printed circuit board by a solder joint. The metal blocks of the prefabricated metal block group are arranged laterally next to one another and have their lateral outer surfaces partially or completely encased by an electrically insulating casing common to them.
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公开(公告)号：US20240292539A1
公开(公告)日：2024-08-29
申请号：US18113414
申请日：2023-02-23
Applicant: Intel Corporation
Inventor： Juha Paavola , Justin M Huttula , Sami Heinisuo , Kari Mansukoski
CPC classification number: H05K1/141 , H05K3/368 , H05K2201/10378
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a standoff interposer between an overlapping portion of a first circuit board and a second circuit board. In selected examples, electronic devices and methods described show one or more conductive pathways within a standoff interposer that provide electrical communication between circuit boards, such as data signals, power delivery, etc.
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Patent Agency Ranking
公开(公告)号：US20240266109A1
公开(公告)日：2024-08-08
申请号：US18625326
申请日：2024-04-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Tomoki KITAGAWA , Tatsunori YASUDA
CPC classification number: H01G2/065 , H01G4/30 , H05K1/116 , H05K2201/10378
Abstract: A multilayer ceramic capacitor includes a capacitor body and an interposer. The capacitor body includes first and second external electrodes. The interposer includes an interposer body and first and second pillars. The interposer body includes an interposer-body first main surface adjacent to the capacitor body, an opposite interposer-body second main surface, and first and second through holes. The first and second pillars each include a metal with a melting point of about 230° C. or higher as a main component, provided in the respective first and second through holes, and conductively connected to the respective first and second external electrodes. The first and second pillars protrude from at least one of the interposer-body first and second main surfaces.
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公开(公告)号：US20240196517A1
公开(公告)日：2024-06-13
申请号：US18585714
申请日：2024-02-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsun JO , Dohoon KIM , Sangyong KIM , Bongkyu MIN , Seoyoung PARK , Yunoh CHI
CPC classification number: H05K1/0219 , H05K1/116 , H05K1/14 , H05K2201/0939 , H05K2201/10378
Abstract: Disclosed is an electronic device. The electronic device includes: a housing, a first board and a second board disposed in an interior of the housing, and an interposer electrically connecting the first board and the second board, the interposer includes a first part that defines an outer surface thereof, and a second part that defines an inner surface thereof, vias included in the first part are all ground vias and are spaced apart from each other by a first interval, and the vias included in the second part include signal vias, and ground vias, the number of which is less than that of the signal vias, and may be spaced apart from each other by a second interval that is larger than or equal to the first interval.
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8.发明公开公开(公告)号：US20240147624A1
公开(公告)日：2024-05-02
申请号：US18498080
申请日：2023-10-31
Applicant: CANON KABUSHIKI KAISHA
Inventor： NORITAKE TSUBOI
CPC classification number: H05K1/181 , H01L25/16 , H05K3/3436 , H05K3/3442 , H05K3/3485 , H05K2201/10015 , H05K2201/10378 , H05K2201/10515 , H05K2201/10636 , H05K2201/10734 , H05K2203/0465
Abstract: An electronic module includes a first wiring component, a first electronic component, a first bonding member, and a second bonding member. The first wiring component includes a first pad, a second pad, and a first insulating member. The first pad, the second pad, and the first insulating member are formed in a first mounting surface. The first electronic component includes a first electrode and a second electrode and is surface-mounted on the first mounting surface. The first bonding member is configured to bond the first pad and the first electrode together. The second bonding member is configured to bond the second pad and the second electrode together. The first electrode and the second electrode are positioned on an insulating area of the first mounting surface. A distance between the first electrode and the first insulating member is smaller than a distance between the first electrode and the first pad.
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9.发明公开公开(公告)号：US20240131339A1
公开(公告)日：2024-04-25
申请号：US18547999
申请日：2022-03-10
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor： Shadi A. Dayeh , Youngbin Tchoe , Andrew M. Bourhis
CPC classification number: A61N1/36125 , A61N1/0531 , H05K1/113 , H05K1/181 , H05K3/32 , H05K2201/041 , H05K2201/10325 , H05K2201/10378 , H05K2203/0384 , H05K2203/1305
Abstract: A flexible electrode array with hundreds or thousands channels for clinical use includes an array of at least hundreds of electrodes on a flexible biocompatible polymer substrate. Perfusion through holes are provided through the substrate. Individual elongate leads connect to each of the electrodes, the elongate lead connections being supported by the flexible biocompatible polymer substrate and extending away from the array. Flexible biocompatible polymer insulates the individual elongate lead connections and supporting the array. An interposer with individual channel connections is conductively bonded to the individual elongate lead connections. Sterile bag packaging encloses a portion of the interposer, where the outer side of the package including the array and individual elongate lead is sterile while the inner side of the packaging is non-sterile. The portion interposer inside the package is configured to connect to a circuit board within the packaging.
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10.发明公开公开(公告)号：US20240107726A1
公开(公告)日：2024-03-28
申请号：US18514331
申请日：2023-11-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyelim YUN , Bongkyu MIN , Dohoon KIM , Taewoo KIM , Jinyong PARK , Jungje BANG , Hyeongju LEE
CPC classification number: H05K9/0032 , H05K1/115 , H05K1/144 , H05K1/181 , H05K7/1427 , H05K2201/10371 , H05K2201/10378
Abstract: An example electronic device includes a printed circuit board on which one or more circuit components are disposed, and an interposer surrounding at least some circuit components of the one or more circuit components and including an inner surface adjacent to the at least some circuit components and an outer surface facing away from the inner surface and having a plurality of through holes. The interposer is disposed on the printed circuit board such that one or more through holes of the plurality of through holes are electrically connected with a ground of the printed circuit board. The outer surface of the interposer includes a first conductive region electrically connected with at least one first through hole of the one or more through holes, and a non-conductive region, the inner surface of the interposer includes a second conductive region electrically connected with at least one second through hole of the one or more through holes, and the second conductive region includes a region facing the non-conductive region.
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