公开(公告)号：US12300918B2

公开(公告)日：2025-05-13

申请号：US17479596

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Navneet Kumar Singh ,  Aiswarya M. Pious ,  Richard S. Perry ,  Amarjeet Kumar ,  Siva Prasad Jangili Ganga ,  Gaurav Hada ,  Sushil Padmanabhan ,  Konika Ganguly

IPC: H01R12/00 ,  H01R12/70 ,  H01R12/73 ,  H01R43/26

Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.

公开(公告)号：US12025971B2

公开(公告)日：2024-07-02

申请号：US17667551

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Navneet Singh ,  Samarth Alva ,  Amarjeet Kumar ,  Gaurav Hada

IPC: G05B19/4155 ,  H01L23/373 ,  H01L23/538 ,  H01R12/70 ,  H05K1/18

CPC classification number: G05B19/4155 ,  H01L23/3736 ,  H01L23/538 ,  H01R12/70 ,  G05B2219/40269 ,  G05B2219/45031 ,  H05K1/181 ,  H05K2201/10378

Abstract: An apparatus includes a memory interposer including a socket including an inner surface, one or more memories disposed on the inner surface, a bottom surface opposite to the inner surface, and pogo pins disposed on the bottom surface and respectively corresponding to the one or more memories, the pogo pins being configured to connect the one or more memories to a printed circuit board (PCB) including a semiconductor die. The apparatus further includes an intermediate thermal head attached to the memory interposer. The memory interposer is movable with respect to the intermediate thermal head.

公开(公告)号：US20240334715A1

公开(公告)日：2024-10-03

申请号：US18126833

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Navneet Kumar Singh ,  Phani Alaparthi ,  Samarth Alva ,  Ritu Bawa ,  Gaurav Hada ,  Aiswarya M. Pious

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/315 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2225/06572

Abstract: Technologies for memory on package with reduced package thickness are disclosed. In the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. The die assembly is mounted on another substrate, such as a mainboard. A cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. Positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.