中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.011 seconds)

    CONFIGURABLE WRITE COMMAND DELAY IN NONVOLATILE MEMORY
    1.
    发明申请
    CONFIGURABLE WRITE COMMAND DELAY IN NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20200174705A1

    公开(公告)日：2020-06-04

    申请号：US16780632

    申请日：2020-02-03

    Applicant: Intel Corporation

    Inventor： Shekoufeh QAWAMI ,  Philip HILLIER ,  Benjamin GRANIELLO ,  Rajesh SUNDARAM

    IPC: G06F3/06

    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

    HARDWARE GUIDANCE FOR EFFICIENTLY SCHEDULING WORKLOADS TO THE OPTIMAL COMPUTE MODULE
    5.
    发明申请
    HARDWARE GUIDANCE FOR EFFICIENTLY SCHEDULING WORKLOADS TO THE OPTIMAL COMPUTE MODULE 有权

    公开(公告)号：US20250061003A1

    公开(公告)日：2025-02-20

    申请号：US18375492

    申请日：2023-09-30

    Applicant: Intel Corporation

    Inventor： Stephen H. GUNTHER ,  Praveen Kumar GUPTA ,  Mahesh Kumar P ,  Monica GUPTA ,  Russell FENGER ,  Benjamin GRANIELLO

    IPC: G06F9/50 ,  G06F11/34

    Abstract: Techniques for providing hardware provided guidance for efficiently scheduling workloads to an optimal compute module are described. In some examples, hardware includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; a power management unit to monitor telemetry data on the first plurality of processor cores and second plurality of processor cores and to update hardware feedback telemetry data; and thread runtime telemetry circuitry to provide a hint using the hardware feedback telemetry data to consolidate tasks on one of core types.

    WRITE DISTURB REFRESH RATE REDUCTION USING WRITE HISTORY BUFFER
    6.
    发明申请
    WRITE DISTURB REFRESH RATE REDUCTION USING WRITE HISTORY BUFFER 有权

    公开(公告)号：US20210110862A1

    公开(公告)日：2021-04-15

    申请号：US17128963

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Akanksha MEHTA ,  Benjamin GRANIELLO ,  Rakan MADDAH ,  Philip HILLIER ,  Richard P. MANGOLD ,  Prashant S. DAMLE ,  Kunal A. KHOCHARE

    IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C15/04

    Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.

Patent Agency Ranking