公开(公告)号：US11714853B2

公开(公告)日：2023-08-01

申请号：US17362554

申请日：2021-06-29

Applicant: Intel Corporation

Inventor： Luis Carlos Maria Remis ,  Vishakha Gupta ,  Christina R. Strong ,  Philip R. Lantz

IPC: G06F16/901 ,  G06F16/903 ,  G06F16/22 ,  G06F16/2455 ,  G06F18/21 ,  G06F18/22 ,  G06V10/96 ,  G06V40/16

CPC classification number: G06F16/901 ,  G06F16/2237 ,  G06F16/24558 ,  G06F16/903 ,  G06F18/21 ,  G06F18/22 ,  G06V10/96 ,  G06V40/172

Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a feature vector index, wherein the feature vector index comprises a sparse-array data structure representing a feature space for a set of labeled feature vectors, wherein the set of labeled feature vectors are assigned to a plurality of classes. The processor is to: receive a query corresponding to a target feature vector; access, via the storage device, a first portion of the feature vector index, wherein the first portion of the feature vector index comprises a subset of labeled feature vectors that correspond to a same portion of the feature space as the target feature vector; determine the corresponding class of the target feature vector based on the subset of labeled feature vectors; and provide a response to the query based on the corresponding class.

公开(公告)号：US11450123B2

公开(公告)日：2022-09-20

申请号：US17374217

申请日：2021-07-13

Applicant: Intel Corporation

Inventor： Christina R. Strong ,  Vishakha Gupta ,  Luis Carlos Maria Remis ,  Kushal Datta ,  Arun Raghunath

IPC: G06T7/11 ,  G06K9/62 ,  G06K15/02 ,  H04N19/176 ,  H04N19/12 ,  H04N19/124 ,  H04N19/513 ,  H04N19/48 ,  G06V30/194 ,  H04N19/167 ,  H04N19/172 ,  H04N19/44 ,  G06T7/20 ,  G06V30/262 ,  G06V10/96 ,  G06V20/00

Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.

公开(公告)号：US11145201B2

公开(公告)日：2021-10-12

申请号：US16733621

申请日：2020-01-03

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Eve M. Schooler ,  Maruti Gupta Hyde ,  Hassnaa Moustafa ,  Katalin Klara Bartfai-Walcott ,  Yen-Kuang Chen ,  Jessica McCarthy ,  Christina R. Strong ,  Arun Raghunath ,  Deepak S. Vembar

IPC: G08G1/09 ,  G06F9/50 ,  G06K9/00 ,  G06Q50/26 ,  G11B27/031 ,  H04N7/18 ,  G08G1/087 ,  G08G1/01 ,  G06F21/60 ,  G06F9/48 ,  G06F21/62 ,  G06K9/62 ,  G06K9/46

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.

公开(公告)号：US11055349B2

公开(公告)日：2021-07-06

申请号：US16235823

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Luis Carlos Maria Remis ,  Vishakha Gupta ,  Christina R. Strong ,  Philip R. Lantz

IPC: G06F16/901 ,  G06F16/903 ,  G06K9/62 ,  G06F16/22 ,  G06F16/2455

Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a feature vector index, wherein the feature vector index comprises a sparse-array data structure representing a feature space for a set of labeled feature vectors, wherein the set of labeled feature vectors are assigned to a plurality of classes. The processor is to: receive a query corresponding to a target feature vector; access, via the storage device, a first portion of the feature vector index, wherein the first portion of the feature vector index comprises a subset of labeled feature vectors that correspond to a same portion of the feature space as the target feature vector; determine the corresponding class of the target feature vector based on the subset of labeled feature vectors; and provide a response to the query based on the corresponding class.

公开(公告)号：US20200250003A1

公开(公告)日：2020-08-06

申请号：US16652038

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Yen-Kuang Chen ,  Ragaad Mohammed Irsehid Altarawneh ,  Juan Pablo Munoz Chiabrando ,  Siew Wen Chin ,  Kushal Datta ,  Subramanya R. Dulloor ,  Julio C. Zamora Esquivel ,  Omar Ulises Florez Choque ,  Vishakha Gupta ,  Scott D. Hahn ,  Rameshkumar Illikkal ,  Nilesh Kumar Jain ,  Siti Khairuni Amalina Kamarol ,  Anil S. Keshavamurthy ,  Heng Kar Lau ,  Jonathan A. Lefman ,  Yiting Liao ,  Michael G. Millsap ,  Ibrahima J. Ndiour ,  Luis Carlos Maria Remis ,  Addicam V. Sanjay ,  Usman Sarwar ,  Eve M. Schooler ,  Ned M. Smith ,  Vallabhajosyula S. Somayazulu ,  Christina R. Strong ,  Omesh Tickoo ,  Srenivas Varadarajan ,  Jesús A. Cruz Vargas ,  Hassnaa Moustafa ,  Arun Raghunath ,  Katalin Klara Bartfai-Walcott ,  Maruti Gupta Hyde ,  Deepak S. Vembar ,  Jessica McCarthy

IPC: G06F9/50 ,  G06K9/00 ,  G06N3/04 ,  G06N3/063

Abstract: In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.

公开(公告)号：US10559202B2

公开(公告)日：2020-02-11

申请号：US16004299

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Eve M. Schooler ,  Maruti Gupta Hyde ,  Hassnaa Moustafa ,  Katalin Klara Bartfai-Walcott ,  Yen-Kuang Chen ,  Jessica McCarthy ,  Christina R. Strong ,  Arun Raghunath ,  Deepak S. Vembar

IPC: G08G1/09 ,  G06F9/50 ,  G06F21/60 ,  G06K9/00 ,  G06F9/48 ,  G06K9/46 ,  G06K9/62 ,  G06Q50/26 ,  G11B27/031 ,  H04N7/18

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.

公开(公告)号：US11887360B2

公开(公告)日：2024-01-30

申请号：US17497287

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Eve M. Schooler ,  Maruti Gupta Hyde ,  Hassnaa Moustafa ,  Katalin Klara Bartfai-Walcott ,  Yen-Kuang Chen ,  Jessica McCarthy ,  Christina R. Strong ,  Arun Raghunath ,  Deepak S. Vembar

IPC: G06V10/82 ,  G06F9/50 ,  G06F21/60 ,  G06V10/44 ,  G06V20/52 ,  G06V40/10 ,  G06F18/241 ,  G06V10/764 ,  G06Q50/26 ,  G08G1/09 ,  G11B27/031 ,  H04N7/18 ,  G08G1/087 ,  G06F9/48 ,  G06F21/62 ,  G06F18/2413 ,  G08G1/01

CPC classification number: G06V10/82 ,  G06F9/4881 ,  G06F9/505 ,  G06F18/241 ,  G06F18/24133 ,  G06F21/604 ,  G06F21/6245 ,  G06Q50/26 ,  G06V10/44 ,  G06V10/764 ,  G06V20/52 ,  G06V40/103 ,  G08G1/091 ,  G11B27/031 ,  H04N7/181 ,  G06F2209/506 ,  G08G1/0116 ,  G08G1/087

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.

公开(公告)号：US11068757B2

公开(公告)日：2021-07-20

申请号：US16142468

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Christina R. Strong ,  Vishakha Gupta ,  Luis Carlos Maria Remis ,  Kushal Datta ,  Arun Raghunath

IPC: G06K9/72 ,  G06K9/00 ,  G06T7/11 ,  G06K9/62 ,  G06K9/66 ,  H04N19/176 ,  H04N19/12 ,  H04N19/124 ,  H04N19/513 ,  H04N19/48 ,  H04N19/167 ,  H04N19/172 ,  H04N19/44 ,  G06T7/20

Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.

公开(公告)号：US20190320022A1

公开(公告)日：2019-10-17

申请号：US16452491

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Arun Raghunath ,  Christina R. Strong

IPC: H04L29/08 ,  G06F3/06

Abstract: In one embodiment, an apparatus comprises processing circuitry to: receive a request from an application to write an image to a data storage system, the request comprising one or more quality of service parameters indicating a level of service requested by the application; partition the image into a plurality of image parts; upload the plurality of image parts to the data storage system in parallel, wherein if the level of service requested by the application comprises low latency: a plurality of redundant copies of each image part is to be uploaded to the data storage system in parallel; and each image part that fails to upload within an upload timeout threshold is to be re-uploaded to the data storage system; receive an acknowledgment from the data storage system that each image part has been uploaded; and notify the application that the image has been written to the data storage system.

公开(公告)号：US20230114468A1

公开(公告)日：2023-04-13

申请号：US17942304

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Christina R. Strong ,  Vishakha Gupta ,  Luis Carlos Maria Remis ,  Kushal Datta ,  Arun Raghunath

IPC: G06F18/24 ,  H04L9/06 ,  G06F21/64 ,  G06F21/53 ,  G06N5/022 ,  G06F21/45 ,  H04L9/32 ,  H04W4/70 ,  G06F21/44 ,  G06F16/538 ,  G06F16/535 ,  G06F16/54 ,  G06F21/62 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06V10/20 ,  G06V10/40 ,  G06V10/75 ,  G06V10/44 ,  G06V20/00 ,  G06V40/20 ,  G06V40/16 ,  G06F9/48 ,  H04L67/51 ,  G06T7/11 ,  G06V10/96 ,  G06V30/262 ,  G06K15/02 ,  G06F18/21 ,  G06F18/22 ,  G06F18/211 ,  G06F18/213 ,  G06F18/2413 ,  G06N3/045 ,  G06N3/08 ,  H04L67/12 ,  H04N19/80 ,  G06F16/951 ,  H04N19/46 ,  G06T7/70

Abstract: In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.