公开(公告)号：US20200250003A1

公开(公告)日：2020-08-06

申请号：US16652038

申请日：2018-06-29

申请人： Intel Corporation

发明人： Shao-Wen Yang ,  Yen-Kuang Chen ,  Ragaad Mohammed Irsehid Altarawneh ,  Juan Pablo Munoz Chiabrando ,  Siew Wen Chin ,  Kushal Datta ,  Subramanya R. Dulloor ,  Julio C. Zamora Esquivel ,  Omar Ulises Florez Choque ,  Vishakha Gupta ,  Scott D. Hahn ,  Rameshkumar Illikkal ,  Nilesh Kumar Jain ,  Siti Khairuni Amalina Kamarol ,  Anil S. Keshavamurthy ,  Heng Kar Lau ,  Jonathan A. Lefman ,  Yiting Liao ,  Michael G. Millsap ,  Ibrahima J. Ndiour ,  Luis Carlos Maria Remis ,  Addicam V. Sanjay ,  Usman Sarwar ,  Eve M. Schooler ,  Ned M. Smith ,  Vallabhajosyula S. Somayazulu ,  Christina R. Strong ,  Omesh Tickoo ,  Srenivas Varadarajan ,  Jesús A. Cruz Vargas ,  Hassnaa Moustafa ,  Arun Raghunath ,  Katalin Klara Bartfai-Walcott ,  Maruti Gupta Hyde ,  Deepak S. Vembar ,  Jessica McCarthy

IPC分类号： G06F9/50 ,  G06K9/00 ,  G06N3/04 ,  G06N3/063

摘要： In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.

公开(公告)号：US09880932B2

公开(公告)日：2018-01-30

申请号：US15688209

申请日：2017-08-28

申请人： Intel Corporation

发明人： Sanjay K. Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/0804 ,  G06F11/14

CPC分类号： G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US10346306B2

公开(公告)日：2019-07-09

申请号：US15089534

申请日：2016-04-02

申请人： Intel Corporation

发明人： Amitabha Roy ,  Subramanya R. Dulloor ,  Rajesh M. Sankaran

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1027

摘要： Methods and apparatuses relating to memory performance monitoring are described, including a processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions. In one embodiment, a processor includes at least one core, a performance monitoring unit, and a memory management unit including a first allocator to allocate a first virtual memory region of a memory for a first data structure, and a second allocator to allocate a second, different virtual memory region of the memory for a second data structure, wherein the memory management unit is to enable the performance monitoring unit to monitor a memory access request from the at least one core when a monitor flag is set for the first virtual memory region or the second, different virtual memory region, and a translation lookaside buffer (TLB) comprising a protection key for a page of a page table, wherein the is to translate a virtual address of the memory access request to a physical address and to set the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored, wherein the memory management unit is to append the monitor flag to the physical address.

公开(公告)号：US20190171396A1

公开(公告)日：2019-06-06

申请号：US16188950

申请日：2018-11-13

申请人： Intel Corporation

发明人： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC分类号： G06F3/06 ,  G06F9/50 ,  G06F12/0888

CPC分类号： G06F3/0673 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0665 ,  G06F9/50 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/1009 ,  G06F2212/60 ,  G06F2212/684

摘要： A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US09690716B2

公开(公告)日：2017-06-27

申请号：US14621654

申请日：2015-02-13

申请人： Intel Corporation

发明人： Sheng Li ,  Sanjay Kumar ,  Victor W. Lee ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor

IPC分类号： G06F12/08 ,  G06F12/1045 ,  G06F12/0891

CPC分类号： G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

摘要： A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

公开(公告)号：US20210141675A1

公开(公告)日：2021-05-13

申请号：US16488576

申请日：2017-04-01

申请人： Intel Corporation

发明人： Shao-Wen Yang ,  Subramanya R. Dulloor ,  Yen-Kuang Chen

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F13/40

摘要： Availability of computing resources is detected on a particular device in a network and a runtime core is caused to be loaded on the particular device based on the availability. The runtime core is configured to support hot-plugging of code embodying any one of a plurality of job and first code comprising a placeholder job is caused to be run on the runtime core to reserve at least a portion of the computing resources of the particular device. A particular one of the plurality of jobs to be run on the particular device is identified and the first code is replaced with second code corresponding to the particular job to replace the placeholder job on the runtime core.

公开(公告)号：US10126985B2

公开(公告)日：2018-11-13

申请号：US14748971

申请日：2015-06-24

申请人： Intel Corporation

发明人： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/0888 ,  G06F9/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0866

摘要： A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US20170357584A1

公开(公告)日：2017-12-14

申请号：US15688209

申请日：2017-08-28

申请人： Intel Corporation

发明人： Sanjay K. KUMAR ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC分类号： G06F12/0804 ,  G06F11/14

CPC分类号： G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US09715453B2

公开(公告)日：2017-07-25

申请号：US14567662

申请日：2014-12-11

申请人： Intel Corporation

发明人： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Dheeraj R. Subbareddy ,  Andrew V. Anderson

IPC分类号： G06F3/06 ,  G06F12/0842 ,  G06F12/02 ,  G06F12/0897 ,  G06F12/1009

CPC分类号： G06F12/0842 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/225 ,  G06F2212/601 ,  G06F2212/7201

摘要： Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

公开(公告)号：US09747208B2

公开(公告)日：2017-08-29

申请号：US15411658

申请日：2017-01-20

申请人： Intel Corporation

发明人： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC分类号： G06F13/00 ,  G06F12/0804 ,  G06F11/14

CPC分类号： G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.