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公开(公告)号：US20200250003A1
公开(公告)日：2020-08-06
申请号：US16652038
申请日：2018-06-29
申请人： Intel Corporation
发明人： Shao-Wen Yang , Yen-Kuang Chen , Ragaad Mohammed Irsehid Altarawneh , Juan Pablo Munoz Chiabrando , Siew Wen Chin , Kushal Datta , Subramanya R. Dulloor , Julio C. Zamora Esquivel , Omar Ulises Florez Choque , Vishakha Gupta , Scott D. Hahn , Rameshkumar Illikkal , Nilesh Kumar Jain , Siti Khairuni Amalina Kamarol , Anil S. Keshavamurthy , Heng Kar Lau , Jonathan A. Lefman , Yiting Liao , Michael G. Millsap , Ibrahima J. Ndiour , Luis Carlos Maria Remis , Addicam V. Sanjay , Usman Sarwar , Eve M. Schooler , Ned M. Smith , Vallabhajosyula S. Somayazulu , Christina R. Strong , Omesh Tickoo , Srenivas Varadarajan , Jesús A. Cruz Vargas , Hassnaa Moustafa , Arun Raghunath , Katalin Klara Bartfai-Walcott , Maruti Gupta Hyde , Deepak S. Vembar , Jessica McCarthy
摘要： In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.
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公开(公告)号：US10417280B2
公开(公告)日：2019-09-17
申请号：US14581112
申请日：2014-12-23
申请人： Intel Corporation
发明人： Xia Zhu , Theodore L. Willke , Bryn Keller , Shih-Chi Chen , Kushal Datta
IPC分类号： G06F17/30 , G06F16/901
摘要： A method, computing system, and computer-readable medium for assigning global edge IDs for evolving graphs are described herein. The method includes selecting a block size for an evolving graph and, as new vertices are added to the evolving graph, calculating block IDs for the evolving graph. Calculating the block IDs includes creating a table representing the evolving graph and, as new vertices are added to the evolving graph, calculating block IDs for cells in a new column of the table before calculating block IDs for cells in a new row of the table. The method also includes calculating global edge IDs for the evolving graph based on the source vertex ID, the target vertex ID, and the block ID for the block at which each edge is located. The method may also include calculating incremental Page Rank for the evolving graph.
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公开(公告)号：US11068757B2
公开(公告)日：2021-07-20
申请号：US16142468
申请日：2018-09-26
申请人： Intel Corporation
IPC分类号： G06K9/72 , G06K9/00 , G06T7/11 , G06K9/62 , G06K9/66 , H04N19/176 , H04N19/12 , H04N19/124 , H04N19/513 , H04N19/48 , H04N19/167 , H04N19/172 , H04N19/44 , G06T7/20
摘要： In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.
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公开(公告)号：US20230114468A1
公开(公告)日：2023-04-13
申请号：US17942304
申请日：2022-09-12
申请人： Intel Corporation
IPC分类号： G06F18/24 , H04L9/06 , G06F21/64 , G06F21/53 , G06N5/022 , G06F21/45 , H04L9/32 , H04W4/70 , G06F21/44 , G06F16/538 , G06F16/535 , G06F16/54 , G06F21/62 , G06F9/50 , G06N3/04 , G06N3/063 , G06V10/20 , G06V10/40 , G06V10/75 , G06V10/44 , G06V20/00 , G06V40/20 , G06V40/16 , G06F9/48 , H04L67/51 , G06T7/11 , G06V10/96 , G06V30/262 , G06K15/02 , G06F18/21 , G06F18/22 , G06F18/211 , G06F18/213 , G06F18/2413 , G06N3/045 , G06N3/08 , H04L67/12 , H04N19/80 , G06F16/951 , H04N19/46 , G06T7/70
摘要： In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.
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公开(公告)号：US20220180651A1
公开(公告)日：2022-06-09
申请号：US17374217
申请日：2021-07-13
申请人： Intel Corporation
IPC分类号： G06V30/262 , G06V10/96 , G06V20/00 , G06T7/11 , G06K9/62
摘要： In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.
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公开(公告)号：US20160179887A1
公开(公告)日：2016-06-23
申请号：US14581964
申请日：2014-12-23
申请人： Intel Corporation
发明人： Todd Lisonbee , Soila P. Kavulya , Bryn Keller , Briton L. Barker , Kushal Datta , Xia Zhu , Theodore L. Willke
IPC分类号： G06F17/30
CPC分类号： G06F17/30958
摘要： A system and method for orchestrating a table operation of data with a graph operation of the data using columnar stores. The orchestration includes storing vertices and edges as collections of tables by type, and supporting the columnar stores with different storage characteristics. The techniques may also include a graph query optimizer that combines chained operators of a graph query; and/or the graph query executed via an in-memory distributed query execution engine.
摘要翻译： 一种用于使用柱状存储使用数据的图形操作来编排数据的表操作的系统和方法。 业务流程包括按照类型将顶点和边存储为表的集合，并支持具有不同存储特性的列存储。 这些技术还可以包括组合图查询的链接运算符的图查询优化器; 和/或通过内存中分布式查询执行引擎执行的图形查询。
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公开(公告)号：US11450123B2
公开(公告)日：2022-09-20
申请号：US17374217
申请日：2021-07-13
申请人： Intel Corporation
IPC分类号： G06T7/11 , G06K9/62 , G06K15/02 , H04N19/176 , H04N19/12 , H04N19/124 , H04N19/513 , H04N19/48 , G06V30/194 , H04N19/167 , H04N19/172 , H04N19/44 , G06T7/20 , G06V30/262 , G06V10/96 , G06V20/00
摘要： In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a plurality of images captured by a camera. The processor: accesses visual data associated with an image captured by the camera; determines a tile size parameter for partitioning the visual data into a plurality of tiles; partitions the visual data into the plurality of tiles based on the tile size parameter, wherein the plurality of tiles corresponds to a plurality of regions within the image; compresses the plurality of tiles into a plurality of compressed tiles, wherein each tile is compressed independently; generates a tile-based representation of the image, wherein the tile-based representation comprises an array of the plurality of compressed tiles; and stores the tile-based representation of the image on the storage device.
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公开(公告)号：US11029971B2
公开(公告)日：2021-06-08
申请号：US16259608
申请日：2019-01-28
申请人： Intel Corporation
发明人： Meenakshi Arunachalam , Kushal Datta , Vikram Saletore , Vishal Verma , Deepthi Karkada , Vamsi Sripathi , Rahul Khanna , Mohan Kumar
摘要： Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.
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公开(公告)号：US20190155620A1
公开(公告)日：2019-05-23
申请号：US16259608
申请日：2019-01-28
申请人： Intel Corporation
发明人： Meenakshi Arunachalam , Kushal Datta , Vikram Saletore , Vishal Verma , Deepthi Karkada , Vamsi Sripathi , Rahul Khanna , Mohan Kumar
摘要： Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.
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公开(公告)号：US10152558B2
公开(公告)日：2018-12-11
申请号：US14581964
申请日：2014-12-23
申请人： Intel Corporation
发明人： Todd Lisobee , Soila P. Kavulya , Bryn Keller , Briton L. Barker , Kushal Datta , Xia Zhu , Theodore L. Willke
IPC分类号： G06F17/30
摘要： A system and method for orchestrating a table operation of data with a graph operation of the data using columnar stores. The orchestration includes storing vertices and edges as collections of tables by type, and supporting the columnar stores with different storage characteristics. The techniques may also include a graph query optimizer that combines chained operators of a graph query; and/or the graph query executed via an in-memory distributed query execution engine.
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