公开(公告)号：US20180174972A1

公开(公告)日：2018-06-21

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US09571059B2

公开(公告)日：2017-02-14

申请号：US14672138

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

IPC: H01P5/12 ,  H03H7/38 ,  H03H7/01 ,  H05K1/02

CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。

公开(公告)号：US10510667B2

公开(公告)日：2019-12-17

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US10910314B2

公开(公告)日：2021-02-02

申请号：US16712091

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US12278175B2

公开(公告)日：2025-04-15

申请号：US17359514

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Xing Jian Cai ,  Chi-Te Chen ,  Wei Qian ,  Yihong Yang ,  Jue Chen ,  Long Wang ,  Chung-Hao Joseph Chen ,  Su Mi Sam ,  Srinivas Thota

IPC: G06F30/20 ,  G05F1/66 ,  G06F30/39 ,  H01L23/50 ,  H01L23/528

Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.

公开(公告)号：US20160285428A1

公开(公告)日：2016-09-29

申请号：US14672138

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

IPC: H03H7/38 ,  H05K1/02 ,  H03H7/01

CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。