公开(公告)号：US20240120651A1

公开(公告)日：2024-04-11

申请号：US17957752

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Tae Young Yang ,  Timo Huusari ,  Renzhi Liu ,  Wei Qian ,  Mengyuan Huang ,  Jason Mix

IPC: H01Q3/26 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01Q3/2676 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6677

Abstract: Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.

公开(公告)号：US20210318561A1

公开(公告)日：2021-10-14

申请号：US17358256

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Meer Nazmus Sakib ,  Saeed Fathololoumi ,  Harel Frish ,  John Heck ,  Eddie Bononcini ,  Reece Defrees ,  Stanley J. Dobek ,  Aliasghar Eftekhar ,  Walter Garay ,  Lingtao Liu ,  Wei Qian

IPC: G02F1/01 ,  G02B6/136 ,  G02B6/132

Abstract: A method may include: forming a base layer on a substrate; forming a waveguide assembly on the base layer, where the waveguide assembly is surrounded by a cladding layer; forming a trench opening through the cladding layer and the base layer; forming an undercut void by etching the substrate through the trench opening, where the undercut void extends under the waveguide assembly and the base layer; and filling the trench opening with a filler to seal off the undercut void. Other embodiments are described and claimed.

公开(公告)号：US20210302652A1

公开(公告)日：2021-09-30

申请号：US17343280

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Boris M. Vulovic ,  Tiehui Su ,  Nutan Gautam ,  Wenhua Lin ,  Mehbuba Tanzid ,  Ansheng Liu ,  Wei Qian

IPC: G02B6/12

Abstract: Techniques for photonic demultiplexers are disclosed. In the illustrative embodiment, an output of an unbalanced interferometer formed from waveguides is positioned to the input of a slab grating, with several output waveguides collecting light in different wavelength ranges to create different channels for the demultiplexer system. In some embodiments, one or more auxiliary structures may be positioned near the input of the grating to change the structure of the spatial modes being provided as an input to the grating in order to alter the spectra of the output channels.

公开(公告)号：US12278175B2

公开(公告)日：2025-04-15

申请号：US17359514

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Xing Jian Cai ,  Chi-Te Chen ,  Wei Qian ,  Yihong Yang ,  Jue Chen ,  Long Wang ,  Chung-Hao Joseph Chen ,  Su Mi Sam ,  Srinivas Thota

IPC: G06F30/20 ,  G05F1/66 ,  G06F30/39 ,  H01L23/50 ,  H01L23/528

Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.

公开(公告)号：US12057386B2

公开(公告)日：2024-08-06

申请号：US17024507

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Wei Qian ,  Cung Tran ,  Sungbong Park ,  John Heck ,  Mark Isenberger ,  Seth Slavin ,  Mengyuan Huang ,  Kelly Magruder ,  Harel Frish ,  Reece Defrees ,  Zhi Li

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L23/528

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

公开(公告)号：US20220276437A1

公开(公告)日：2022-09-01

申请号：US17747929

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Boris Vulovic ,  Wenhua Lin ,  Wei Qian ,  Tiehui Su ,  Nutan Gautam ,  Mehbuba Tanzid ,  Hao-Hsiang Liao

IPC: G02B6/12 ,  G02B6/122

Abstract: Thermally compensated waveguides are disclosed herein. According to one aspect, the present disclosure proposes new ways to combine negative TOC (NTOC) material layers within the waveguides. NTOC materials can be implemented in one or more of a cladding layer, a core rib/channel waveguide, a horizontally segmented waveguide, a vertically segmented waveguide, a sub-wavelength grating structure, and/or in various other waveguide structure implementations including arbitrary core or cladding shapes. The integration of NTOC materials improves the temperature dependence of the waveguide spectrum. The need for fast and efficient optical-based technologies is increasing as Internet data traffic growth rate is overtaking voice traffic, pushing the need for optical communications. The new waveguide structures can be integrated into waveguides, individual devices, integrated devices like arrayed waveguide grating devices, and photonic integration circuits (PICs), decreasing temperature dependence of such devices and circuits.

公开(公告)号：US20220019098A1

公开(公告)日：2022-01-20

申请号：US17131470

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Mengyuan Huang ,  David Patel ,  Kejia Li ,  Wei Qian ,  Ansheng Liu

IPC: G02F1/025

Abstract: An optical modulator includes a substrate, a first dielectric layer over the substrate, a rib waveguide including a PN junction on the first dielectric, a second dielectric layer over the rib waveguide and a stressor layer including a metal, where the first or the second dielectric is between the stressor layer and the PN junction.

公开(公告)号：US11940678B2

公开(公告)日：2024-03-26

申请号：US17131470

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Mengyuan Huang ,  David Patel ,  Kejia Li ,  Wei Qian ,  Ansheng Liu

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2201/063 ,  G02F2202/105

Abstract: An optical modulator includes a substrate, a first dielectric layer over the substrate, a rib waveguide including a PN junction on the first dielectric, a second dielectric layer over the rib waveguide and a stressor layer including a metal, where the first or the second dielectric is between the stressor layer and the PN junction.

公开(公告)号：US11906777B2

公开(公告)日：2024-02-20

申请号：US16797657

申请日：2020-02-21

Applicant: Intel Corporation

Inventor： John Heck ,  Lina He ,  Sungbong Park ,  Olufemi Isiade Dosunmu ,  Harel Frish ,  Kelly Christopher Magruder ,  Seth M. Slavin ,  Wei Qian ,  Ansheng Liu ,  Nutan Gautam ,  Mark Isenberger

IPC: G02B6/12 ,  H04J14/02 ,  G02B6/122

CPC classification number: G02B6/12007 ,  G02B6/12004 ,  G02B6/1228 ,  H04J14/02 ,  G02B2006/12061

Abstract: Embodiments may relate to a wavelength-division multiplexing (WDM) transceiver that has a silicon waveguide layer coupled with a silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may include a tapered portion that is coupled with the silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may be coupled with a first oxide layer with a first z-height, and the silicon nitride waveguide layer may be coupled with a second oxide layer with a second z-height that is greater than the first z-height. Other embodiments may be described or claimed.

公开(公告)号：US20220416097A1

公开(公告)日：2022-12-29

申请号：US17358921

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： David Kohen ,  Kelly Magruder ,  Parastou Fakhimi ,  Zhi Li ,  Cung Tran ,  Wei Qian ,  Mark Isenberger ,  Mengyuan Huang ,  Harel Frish ,  Reece DeFrees ,  Ansheng Liu

IPC: H01L31/0232 ,  G02B6/12 ,  H01L31/105 ,  H01L31/107 ,  H01L31/18

Abstract: A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.