公开(公告)号：US10229887B2

公开(公告)日：2019-03-12

申请号：US15087270

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/285 ,  H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L21/784 ,  H01L23/29 ,  H01L21/683 ,  H01L21/56

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20180174972A1

公开(公告)日：2018-06-21

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US20170250145A1

公开(公告)日：2017-08-31

申请号：US15595581

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/60 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US20170179040A1

公开(公告)日：2017-06-22

申请号：US14978294

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/552 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US10910314B2

公开(公告)日：2021-02-02

申请号：US16712091

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US10763220B2

公开(公告)日：2020-09-01

申请号：US16256338

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/285 ,  H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L23/29 ,  H01L21/683 ,  H01L21/784 ,  H01L21/56

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20180166363A1

公开(公告)日：2018-06-14

申请号：US15579116

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Joshua D. Heppner ,  Mitul B. Modi

IPC: H01L23/48 ,  H01L23/552 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/768 ,  H01L23/48 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2924/19107

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.

公开(公告)号：US10510667B2

公开(公告)日：2019-12-17

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US20190157215A1

公开(公告)日：2019-05-23

申请号：US16256338

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L21/285 ,  H01L23/29 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/784 ,  H01L21/78 ,  H01L23/544

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20170287846A1

公开(公告)日：2017-10-05

申请号：US15087270

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/285

CPC classification number: H01L23/552 ,  H01L21/2855 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L21/784 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10155 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.