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    Device, system and method to interconnect circuit components on a transparent substrate
    7.
    发明授权
    Device, system and method to interconnect circuit components on a transparent substrate 有权

    公开(公告)号：US10269716B2

    公开(公告)日：2019-04-23

    申请号：US15201337

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Vijay Kasturi ,  Ana M. Yepes ,  Chung-Hao Chen ,  Bradley A. Jackson

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15

    Abstract: Techniques and mechanisms for interconnecting circuitry disposed on a transparent substrate. In an embodiment, a multilayer circuit is bonded to the transparent substrate, the multilayer circuit including conductive traces that are variously offset at different respective levels from a side of the transparent substrate. Circuit components, such as packaged or unpackaged integrated circuit devices, are coupled each to respective input and/or output (IO) contacts of the multilayer circuit, where the conductive traces and the IO contacts interconnect the circuit components with each other. In another embodiment, the multilayer circuit is a flexible circuit that is bent to interconnect circuit components which are disposed on opposite respective sides of the transparent substrate.

    Parallel via to improve the impedance match for embedded common mode filter design
    8.
    发明授权
    Parallel via to improve the impedance match for embedded common mode filter design 有权
    并联通过改善嵌入式共模滤波器设计的阻抗匹配

    公开(公告)号：US09571059B2

    公开(公告)日：2017-02-14

    申请号：US14672138

    申请日：2015-03-28

    Applicant: Intel Corporation

    Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

    IPC: H01P5/12 ,  H03H7/38 ,  H03H7/01 ,  H05K1/02

    CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

    Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

    Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。

    Integration of millimeter wave antennas in reduced form factor platforms
    10.
    发明授权
    Integration of millimeter wave antennas in reduced form factor platforms 有权

    公开(公告)号：US10522898B2

    公开(公告)日：2019-12-31

    申请号：US15756923

    申请日：2016-08-30

    Applicant: INTEL CORPORATION

    Inventor： Min Keen Tang ,  Ana M. Yepes ,  Yaniv Michaeli ,  Menashe Soffer

    IPC: H01Q1/38 ,  H01Q1/22 ,  H01Q1/48 ,  H01Q9/04 ,  H01Q21/28

    Abstract: Generally, this disclosure provides systems, devices and methods for integration of millimeter wave antennas in platforms with reduced form factors while maintaining or improving antenna gain. An antenna assembly may include a first planar substrate; a ground plane disposed on the first planar substrate; a second planar substrate disposed on the ground plane; and an antenna radiation element disposed on the second planar substrate. The antenna radiation element may be configured to transmit a signal in the millimeter wave frequency region. The assembly may also include a via to provide a conductive path for the signal from a microstrip feed line, beneath the first planar substrate, to the antenna radiation element. The assembly may further include a dielectric layer disposed on the antenna radiation element to provide increased antenna gain under conditions of reduced air gap between the antenna radiation element and a structural element of an enclosing platform.

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