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    DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES
    2.
    发明申请
    DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES 审中-公开

    公开(公告)号：US20200265545A1

    公开(公告)日：2020-08-20

    申请号：US16853405

    申请日：2020-04-20

    Applicant: Intel Corporation

    Inventor： Naveen MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

    IPC: G06T1/20 ,  G06N3/08 ,  G06N3/04 ,  G06F7/544 ,  G06F17/15 ,  G06F7/501 ,  G06F5/01 ,  G06F7/523 ,  G06F17/16 ,  G06N3/063

    Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

    FINE-GRAIN COMPUTE COMMUNICATION EXECUTION FOR DEEP LEARNING FRAMEWORKS
    6.
    发明申请
    FINE-GRAIN COMPUTE COMMUNICATION EXECUTION FOR DEEP LEARNING FRAMEWORKS 审中-公开

    公开(公告)号：US20180322386A1

    公开(公告)日：2018-11-08

    申请号：US15869502

    申请日：2018-01-12

    Applicant: Intel Corporation

    Inventor： SRINIVAS SRIDHARAN ,  DHEEVATSA MUDIGERE

    IPC: G06N3/08 ,  G06N3/04 ,  G06T15/00

    CPC classification number: G06N3/08 ,  G06F9/54 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

    Abstract: One embodiment provides for a system to configure distributed training of a neural network. The system includes memory to store a library to facilitate transmission of data during distributed training of the neural network; a network interface to transmit and receive gradient data associated with the trainable parameters; a general-purpose processor to execute instructions provided by the library, the instructions to cause the general-purpose processor to configure the network interface to transmit and receive the gradient data associated with the trainable parameters during a workflow of a machine learning framework; and a graphics processor to perform compute operations associated with machine learning framework workflow to generate the gradient data associated with the trainable parameters, wherein, based on the machine learning framework workflow, the library is to interleave the compute operations on the graphics processor with transmission and receipt of gradient data via the network interface.

    DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES
    8.
    发明申请
    DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES 有权

    公开(公告)号：US20210110508A1

    公开(公告)日：2021-04-15

    申请号：US17083588

    申请日：2020-10-29

    Applicant: Intel Corporation

    Inventor： Naveen MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  DIPANKAR DAS ,  SRINIVAS SRIDHARAN

    IPC: G06T1/20 ,  G06N3/063 ,  G06F17/16 ,  G06F7/523 ,  G06F5/01 ,  G06F7/501 ,  G06F17/15 ,  G06N3/04 ,  G06F7/544 ,  G06N3/08

    Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

    INCREMENTAL PRECISION NETWORKS USING RESIDUAL INFERENCE AND FINE-GRAIN QUANTIZATION
    10.
    发明申请
    INCREMENTAL PRECISION NETWORKS USING RESIDUAL INFERENCE AND FINE-GRAIN QUANTIZATION 审中-公开

    公开(公告)号：US20180314940A1

    公开(公告)日：2018-11-01

    申请号：US15869515

    申请日：2018-01-12

    Applicant: Intel Corporation

    Inventor： Abhisek KUNDU ,  NAVEEN MELLEMPUDI ,  DHEEVATSA MUDIGERE ,  Dipankar DAS

    IPC: G06N3/08 ,  G06T15/00 ,  G06N5/04

    Abstract: One embodiment provides for a computing device comprising a parallel processor compute unit to perform a set of parallel integer compute operations; a ternarization unit including a weight ternarization circuit and an activation quantization circuit; wherein the weight ternarization circuit is to convert a weight tensor from a floating-point representation to a ternary representation including a ternary weight and a scale factor; wherein the activation quantization circuit is to convert an activation tensor from a floating-point representation to an integer representation; and wherein the parallel processor compute unit includes one or more circuits to perform the set of parallel integer compute operations on the ternary representation of the weight tensor and the integer representation of the activation tensor.

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