公开(公告)号：US12158852B2

公开(公告)日：2024-12-03

申请号：US17358832

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Bharadwaj Krishnamurthy ,  Shruti Sharma ,  Byoungchan Oh ,  Jing Fang ,  Daniel Klowden ,  Jason Howard ,  Joshua Fryman

IPC: G06F13/28

Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields.

公开(公告)号：US20240355980A1

公开(公告)日：2024-10-24

申请号：US18305525

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Daniel Klowden ,  Joshua Fryman

IPC: H01L33/62 ,  H01L33/58

CPC classification number: H01L33/62 ,  H01L33/58

Abstract: An IC package may include a stack of microelectronic units capable of horizontal and vertical optical communications. A microelectronic unit includes one or more power delivery pillars, two light source layers, an optical interconnect layer between the light source layers, and one or more IC devices arranged on the optical interconnect layer. A light source layer includes micro-LEDs that emit light used for generating optical signals. The optical interconnect layer includes one or more optical interconnects that enable horizontal optical communication, e.g., transmission of optical signals between the IC devices. A light source layer in the microelectronic unit can facilitate optical communications with another microelectronic unit that is below or above the microelectronic unit. A channel may exist above or below the light source layer to promote dissipation of heat generated by the IC devices. Light from the light source layer may pass through the channel for vertical optical communication.

公开(公告)号：US11983135B2

公开(公告)日：2024-05-14

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Anshuman Thakur ,  Md Altaf Hossain ,  Mahesh Kumashikar ,  Kemal Aygün ,  Casey Thielen ,  Daniel Klowden ,  Sandeep B. Sane

IPC: G06F13/42 ,  G06F30/30 ,  G06F30/347

CPC classification number: G06F13/4221 ,  G06F13/4282 ,  G06F30/30 ,  G06F30/347 ,  G06F2213/0026

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.