公开(公告)号：US12035507B2

公开(公告)日：2024-07-09

申请号：US17723099

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Scott Rider ,  Devdatta Kulkarni

IPC: H05K7/20 ,  H01L23/24 ,  H01L23/34 ,  H01L25/065

CPC classification number: H05K7/20254 ,  H01L23/34 ,  H01L25/065

Abstract: Technologies for dynamic cooling include a computing device having a multi-chip package including multiple dies and a cold plate coupled to the multi-chip package. Micro nozzle valves are coupled to fluid passage zones of the cold plate positioned adjacent to the dies, and are configured to control fluid flow into the fluid passage zones. The computing device reads a predetermined die junction temperature for each die, determines a current die junction temperature for each die, compares the predetermined die junction temperature to the current die junction temperature for each die, and determines a fluid flow rate for each die based on that comparison. The computing device controls the micro nozzle valves adjacent to each die based on the respective fluid flow rate. The dies may include processor cores, field-programmable gate arrays, memory devices, or other computer chips. Other embodiments are described and claimed.

公开(公告)号：US20230025921A1

公开(公告)日：2023-01-26

申请号：US17957175

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Devdatta Kulkarni ,  Alexey Chinkov ,  Brian Jarrett ,  Jeff King ,  John Gulick

IPC: H05K7/20

Abstract: Cold plates and liquid cooling systems for electronic devices are disclosed herein. An example cold plate includes a body defining a cavity. The body has an inlet opening and an outlet opening fluidically coupled to the cavity such that a fluid passageway is defined between the inlet opening and the outlet opening. The cold plate also includes metal foam in the cavity.

公开(公告)号：US10468331B2

公开(公告)日：2019-11-05

申请号：US15869700

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Je-young Chang ,  Jae W. Kim ,  Ravindranath V. Mahajan ,  Blake Rogers ,  Devdatta Kulkarni

IPC: H01L23/48 ,  H01L23/473 ,  F28D9/00 ,  B23P15/26 ,  F28D21/00 ,  H01L23/28 ,  H01L23/00 ,  G06F1/20

Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface.The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.

公开(公告)号：US20230253288A1

公开(公告)日：2023-08-10

申请号：US17668236

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Abdulafeez Adebiyi ,  Je-Young Chang ,  Devdatta Kulkarni ,  Sandeep Ahuja

IPC: H01L23/373 ,  H01L23/427 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3733 ,  H01L23/427 ,  H01L25/0655 ,  H01L21/4871 ,  H01L21/56 ,  H01L23/291 ,  H01L23/29 ,  H01L23/3732 ,  H01L24/13

Abstract: An integrated circuit device may include an integrated circuit die coupled to a substrate, and a porous material on the die or a thermal interface material and extending beyond the edges of the die and over the substrate. An integrated circuit system may include a substrate with a power supply and an integrated circuit die, such that a porous material on the die extends over the substrate beyond a footprint of the die. A porous material may be formed on and beyond an edge of a received integrated circuit die coupled to a substrate or a thermal interface material on the die.

公开(公告)号：US20230125822A1

公开(公告)日：2023-04-27

申请号：US17512138

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Abdulafeez Adebiyi ,  Je-Young Chang ,  Devdatta Kulkarni

IPC: H01L23/44 ,  H01L23/373

Abstract: A two-phase immersion cooling system for integrated circuit assembly may be formed utilizing a heat dissipation device thermally coupled to at least one integrated circuit device, wherein the heat dissipation device may include a surface enhancement structure and a boiling enhancement material layer, such as a micro-porous material, on the surface enhancement structure.

公开(公告)号：US20220240417A1

公开(公告)日：2022-07-28

申请号：US17723099

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Scott Rider ,  Devdatta Kulkarni

IPC: H05K7/20 ,  H01L23/34 ,  H01L25/065

Abstract: Technologies for dynamic cooling include a computing device having a multi-chip package including multiple dies and a cold plate coupled to the multi-chip package. Micro nozzle valves are coupled to fluid passage zones of the cold plate positioned adjacent to the dies, and are configured to control fluid flow into the fluid passage zones. The computing device reads a predetermined die junction temperature for each die, determines a current die junction temperature for each die, compares the predetermined die junction temperature to the current die junction temperature for each die, and determines a fluid flow rate for each die based on that comparison. The computing device controls the micro nozzle valves adjacent to each die based on the respective fluid flow rate. The dies may include processor cores, field-programmable gate arrays, memory devices, or other computer chips. Other embodiments are described and claimed.

公开(公告)号：US20220015262A1

公开(公告)日：2022-01-13

申请号：US16924789

申请日：2020-07-09

Applicant: Intel Corporation

Inventor： Scott Rider ,  Devdatta Kulkarni

IPC: H05K7/20 ,  H01L25/065 ,  H01L23/34 ,  G06F1/20

Abstract: Technologies for dynamic cooling include a computing device having a multi-chip package including multiple dies and a cold plate coupled to the multi-chip package. Micro nozzle valves are coupled to fluid passage zones of the cold plate positioned adjacent to the dies, and are configured to control fluid flow into the fluid passage zones. The computing device reads a predetermined die junction temperature for each die, determines a current die junction temperature for each die, compares the predetermined die junction temperature to the current die junction temperature for each die, and determines a fluid flow rate for each die based on that comparison. The computing device controls the micro nozzle valves adjacent to each die based on the respective fluid flow rate. The dies may include processor cores, field-programmable gate arrays, memory devices, or other computer chips. Other embodiments are described and claimed.