公开(公告)号：US20240136244A1

公开(公告)日：2024-04-25

申请号：US18395351

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/49568

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US11664294B2

公开(公告)日：2023-05-30

申请号：US16241158

申请日：2019-01-07

Applicant: INTEL CORPORATION

Inventor： Aastha Uppal ,  Je-Young Chang ,  Weihua Tang ,  Minseok Ha

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/427 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/427 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/09 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L2924/14

Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.

公开(公告)号：US20210235596A1

公开(公告)日：2021-07-29

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US20200227341A1

公开(公告)日：2020-07-16

申请号：US16246311

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Je-Young Chang ,  Jae Kim ,  Ravindranath Mahajan

IPC: H01L23/433 ,  F28F3/12 ,  F28F9/00 ,  F28F9/02 ,  H01L23/367 ,  H01L23/473

Abstract: A heat exchange module, comprising an array of microchannels, where the array of microchannels extends in a first direction, and are separated from one another by a first sidewall. The array of microchannels is over a cold plate. A first array of fluid distribution channels is stacked over the array of microchannels and extend in a second direction that is substantially orthogonal to the first direction. The first array of fluid distribution channels extends from the first manifold and terminate between a first manifold and a second manifold. A second array of fluid distribution channels is stacked over the array of microchannels. The first array of fluid distribution channels and the second array of the fluid distribution channels are fluidically coupled to the microchannel array. A wall extends into the microchannel array below a second sidewall separating ones of the first array and ones of the second array of fluid distribution channels.

公开(公告)号：US20190004573A1

公开(公告)日：2019-01-03

申请号：US15637439

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Devdatta P. Kulkarni ,  Richard J. Dischler ,  Je-Young Chang

IPC: G06F1/20 ,  H01L23/367 ,  H01L23/495 ,  H01L21/02

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.

公开(公告)号：US20160007499A1

公开(公告)日：2016-01-07

申请号：US14856836

申请日：2015-09-17

Applicant: Intel Corporation

Inventor： David W. Song ,  Je-Young Chang

IPC: H05K7/20

CPC classification number: H05K7/20272 ,  H01L23/427 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H05K1/0209 ,  H05K7/20218 ,  H05K7/2039 ,  H05K2201/066 ,  Y10T29/4913

Abstract: A heat dissipation lid that includes a plate having a first surface, an opposing second surface, and at least one sidewall extending from the plate second surface. The heat dissipation lid also includes at least one fluid delivery conduit and at least one fluid removal conduit, each extending between the plate first and second surface, and at least one spacing projection extending from the plate second surface to establish and maintain a desired distance between the plate second surface and a microelectronic device, when the heat dissipation lid is positioned to remove heat from the microelectronic device.

Abstract translation: 一种散热盖，其包括具有第一表面，相对的第二表面和从所述板第二表面延伸的至少一个侧壁的板。 散热盖还包括至少一个流体输送管道和至少一个流体移除管道，每个至少一个流体移除管道在板的第一和第二表面之间延伸，以及至少一个从板的第二表面延伸的间隔突起，以建立和保持 板的第二表面和微电子器件，当散热盖定位成从微电子器件移除热量时。

公开(公告)号：US12048123B2

公开(公告)日：2024-07-23

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US11670561B2

公开(公告)日：2023-06-06

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu ,  Liwei Wang

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/42 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11322456B2

公开(公告)日：2022-05-03

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Venkata Suresh R. Guthikonda ,  Shankar Devasenathipathy ,  Chandra M. Jha ,  Je-Young Chang ,  Kyle Yazzie ,  Prasanna Raghavan ,  Pramod Malatkar

IPC: H05K1/18 ,  H01L23/00 ,  H01L21/50 ,  H01L23/544 ,  H01L25/065 ,  H05K1/02

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.