公开(公告)号：US20240385754A1

公开(公告)日：2024-11-21

申请号：US18570674

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Daocheng BU ,  Dujian WU ,  Yufu LI ,  Vincent ZIMMER

IPC: G06F3/06

Abstract: Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.

公开(公告)号：US20180314568A1

公开(公告)日：2018-11-01

申请号：US15770790

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Yuping YANG ,  Dujian WU ,  Shijie LIU ,  Daquan DONG

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/455 ,  G06F9/4401

CPC classification number: G06F9/542 ,  G06F2209/542

Abstract: A method includes modifying a basic input/output system (BIOS) to load a virtual general purpose input/output (GPIO) driver in an operating system, the virtual GPIO driver comprising at least one control method to monitor a system control interrupt (SCI) (202). The method can also include detecting the system control interrupt invoking the virtual GPIO driver (204) and executing the control method corresponding to the system control interrupt, the control method to be identified in the modified BIOS (206). Furthermore, the method can include detecting an error from the execution of the control method (208) and modifying an operating system to prevent the error (208), the modification Execute the Control Method Corresponding to the System Control comprising a modification to the control method.

公开(公告)号：US20220093197A1

公开(公告)日：2022-03-24

申请号：US17421483

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Dujian WU ,  Shijian GE ,  Daocheng BU

IPC: G11C29/10 ,  G11C29/12 ,  G11C29/46 ,  G11C29/38

Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.