公开(公告)号：US20220029838A1

公开(公告)日：2022-01-27

申请号：US17481771

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Uri Bear ,  Reuven Elbaum ,  Elad Peer

IPC: H04L9/32

Abstract: The disclosure generally provides methods, systems and apparatus to construct a Physically Unclonable Function (PUF) value for an electronic package based on the package's internal components and their interconnects. In one embodiment, the package is a System-On-Chip (SOC) having a plurality of dielets and a plurality of interconnect connecting the dielets. Each of the dielets and each of the interconnects (at one or more locations) may define an entropy source. each entropy source may have an entropy value. Each entropy source communicates an initial entropy value to a PUF aggregator. The PUF aggregator receives and/or aggregates the various entropies from the various entropy sources to construct the native SOC PUF value. The native SOC PUF value defines the authentic PUF value of the SOC at SOC release. Any deviation from the native SOC PUF value may be deemed a security breach of the SOC.

公开(公告)号：US20190004972A1

公开(公告)日：2019-01-03

申请号：US15637524

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Uri Bear ,  Gyora Benedek ,  Baruch Chaikin ,  Jacob Jack Doweck ,  Reuven Elbaum ,  Dimitry Kloper ,  Elad Peer ,  Chaim Shen-orr ,  Yonatan Shlomovich

IPC: G06F12/14 ,  G06F12/1009

Abstract: Various systems and methods for detecting and preventing side-channel attacks, including attacks aimed at discovering the location of KASLR-randomized privileged code sections in virtual memory address space, are described. In an example, a computing system includes electronic operations for detecting unauthorized attempts to access kernel virtual memory pages via trap entry detection, with operations including: generating a trap page with a physical memory address; assigning a phantom page at an open location in the privileged portion of the virtual memory address space; generating a plurality of phantom page table entries corresponding to an otherwise-unmapped privileged virtual memory region; placing the trap page in physical memory and placing the phantom page table entry in a page table map; and detecting an access to the trap page via the phantom page table entry, to trigger a response to a potential attack.

公开(公告)号：US20250021630A1

公开(公告)日：2025-01-16

申请号：US18900225

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Aviv Barkai ,  Benjamin Zeltser ,  Elad Peer

IPC: G06F21/12

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to prevent attacks on software. An example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: insert a plurality of code blocks into an input code; insert replacement manager instructions into the input code, the replacement manager instructions to, when executed: determine a subset of the plurality of code blocks; and insert the subset of the plurality of code blocks into memory for execution during execution of the input code.

公开(公告)号：US11194933B2

公开(公告)日：2021-12-07

申请号：US16431153

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Yaacov Belenky ,  Gyora Benedek ,  Reuven Elbaum ,  David Novick ,  Elad Peer ,  Chaim Shen-Orr ,  Yonatan Shlomovich

IPC: H04L29/06 ,  G06F21/72 ,  H04L9/08 ,  G06F21/60 ,  G06F21/56 ,  H04L9/06 ,  H04L9/00

Abstract: The present disclosure is directed to systems and methods to protect against SCA and fault injection attacks through the use of a temporary or ephemeral key to cryptographically alter input data portions. Universal resistant block (URB) circuitry receives a seed data value and a at least one secret key data value and generates an ephemeral key output data value. Cryptographic circuitry uses the ephemeral key data value to transform an input data portion to produce an transformed output data portion. The use of an SCA or fault injection attack on the transformed output data portion will reveal only the ephemeral key data value and not the at least one secret key data value. Further, where a unique ephemeral key data value is used to transform each input data portion, an attacker cannot discover the ephemeral key in a piecemeal manner and must instead discover the complete ephemeral key data value—significantly increasing the difficulty of performing a successful SCA or fault injection attack.

公开(公告)号：US20210020775A1

公开(公告)日：2021-01-21

申请号：US17033444

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Uri Bear ,  Elad Peer ,  Elena Sidorov ,  Rami Sudai ,  Reuven Elbaum ,  Steve J. Brown

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04

Abstract: In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

公开(公告)号：US11984512B2

公开(公告)日：2024-05-14

申请号：US17033444

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Uri Bear ,  Elad Peer ,  Elena Sidorov ,  Rami Sudai ,  Reuven Elbaum ,  Steve J. Brown

IPC: H01L29/788 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B43/00

CPC classification number: H01L29/788 ,  G11C16/0408 ,  H01L29/42324 ,  H01L29/66825 ,  H10B41/00 ,  H10B43/00

Abstract: In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.