公开(公告)号：US20220222194A1

公开(公告)日：2022-07-14

申请号：US17711986

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Neelam CHANDWANI ,  Shridhar BENDI ,  Rajesh VIVEKANANDHAM ,  Rahul PAL ,  Eric J. DAHLEN ,  Antonio J. HASBUN MARIN ,  Chung-Chi WANG ,  Qian LI ,  Hosein NIKOPOUR ,  Sravanthi KOTA VENKATA ,  Rajesh POORNACHANDRAN ,  Udayan MUKHERJEE

IPC: G06F13/40 ,  G06F13/16

Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

公开(公告)号：US20180004432A1

公开(公告)日：2018-01-04

申请号：US15633571

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Eric J. DAHLEN ,  Glenn J. HINTON ,  Raj K. RAMANUJAN

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/0868 ,  G06F12/02 ,  G06F12/06 ,  G11C14/00 ,  G06F11/07

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.